Hi team,
Can you please help review the TPS7B8601BQDDARQ1 SCH as attached?
Customer pull-up the PG pin to sys_3v3, and the sys_3v3 sequence is ealier than SOC_A2B_8V_EN. Is there any risk here?
Thank you
Best Regards,
Xiaowei Zhang
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi team,
Can you please help review the TPS7B8601BQDDARQ1 SCH as attached?
Customer pull-up the PG pin to sys_3v3, and the sys_3v3 sequence is ealier than SOC_A2B_8V_EN. Is there any risk here?
Thank you
Best Regards,
Xiaowei Zhang
Hi Xiaowei Zhang,
The device looks good to me and should function as expected. Pins configured correctly, elements within acceptable ranges, etc.
The only concern with the PG pullup rail being sequenced before the LDO is that if VIN isn't high enough to power the logic it may not be able to drive the gate on the open drain PG FET. The high impedance would look like a PG high output before the LDO turns on. I can confirm if it will or will not do that. If VIN is sufficiently high, and only EN is sequenced after sys_3v3, then it should not have any issues.
Best,
Gregory Thompson