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TPS6593-Q1: Voltage on GPIO pins

Daisuke Maeda
Guru 20305 points
Part Number: TPS6593-Q1
Other Parts Discussed in Thread: SK-AM62A-LP, AM62A7

I checked the following user guide and the datasheet for the power connections with AM62A.

TPS65931211-Q1 PMIC User Guide for AM62A
www.ti.com/.../slvucm3.pdf

The datasheet describes that a GPIO pin configured as Open-drain (GPIO5_OD = 0x1) can be pulled up to VIO.

Can a GPIO pin configured as input (GPIO1_DIR = 0x0) be pulled up to VIO?

If so, does a GPIO pin need to be configured as input (GPIO1_DIR = 0x0) and Open-drain (GPIO5_OD = 0x1)?

Best regards,

Daisuke

 

  • 0
    TI__Guru* 79721 points

    Hi Daisuke,

    The user's guide that you reference is specific for TPS65931211-Q1 configuration. In that configuration, the GPIO5 is being used as an input to select which LDO1 voltage you want to be output, either 3.3V or 1.8V. It is configured as an input with internal pulldown, and then you need to pull it up externally to create the selection of 3.3V if that is what you are wanting on LDO1. It has a rising and falling edge trigger into the PFSM state machine, as shown in section 6.2 PFSM Triggers.

    I believe the reason that the GPIO5_OD is set to 1 is only for when you set GPIO5 as an output, and likely in this case it is configured open drain in case this pin is accidentally selected as output during operation - because a voltage could be being applied on the pin, you would not want to accidentally be driving opposite value/cause a short or other issue. 

    I wanted to back up a step and ask the reason behind your question - what is your intended GPIO use case and for which GPIO? Are you working on a custom config? 

    Regards,

    Katie

  • 0 in reply to Katie Pier
    Guru 20305 points

    Hi Katie-san,

    Thank you for your reply.

    My first post contained several typos. It is not the questions about specific GPIO pins (GPIO1 and GPIO5). I want to clarify the power sources that can be connected for each of the IO signals requiring a pull-up.

    Can the IO pins configured as input be connected to VIO (3.3V)?

    If not, then they should be connected to 1.8V.

    Can they be connected to BUCK5 (1.8V)?

    If not, does 1.8V need to be derived by dividing 3.3V?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    So seeing the Table 3-3. Digital Connections by System Feature in the User's Guide for the required feature set.

    For the connections for the GPIOs please see the sprr459b AM62A LP EVM, specifically the E2 design schematic, you will see the connections needed beyond the PMIC for features.

    GPIO3: See EVM for external connection *

    GPIO5: Pulled up to VIO_IN source with a 10K resistor or grounded

    GPIO6: Can be left floating/grounded, or pulled up to VIO_IN source with a 10k resistor.

    GPIO7: See EVM for external connection *

    GPIO9: See EVM for external connection * 

    GPIO10: Can be left floating/grounded, or pulled up to VIO_IN source with a 10k resistor. The EVM grounds this pin.

    GPIO11: See EVM for external connection * 

    * External PU requirement is determined by SoC or Glue logic, see EVM for connection

    Best Regards,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your reply.

    I checked the connections of the IO pins on SK-AM62A-LP (PROC135A1). Most of them were pulled up to 3.3V (same voltage level as VIO_IN).

    Can the IO pins below with the specified configuration really be pulled-up to 3.3V?

    For GPIO3/4/5/6, they use the VRTC or VINT domain. The voltage on the logic pins is 1.8V under the recommended operating conditions.

    For I2C and SPI pins and other GPIO pins, the voltage on those logic pins in VIO domain is the same as VIO_IN under the recommended operating conditions. But they use the VINT domain as input.

    Best regards,

    Daisuke

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your support. Our customer is waiting for your reply.

    I assume that the IO pins configured as input, which I highlighted in yellow in my previous post, can be pulled up to 3.3V (VIO_IN).

    Is my assumption correct?

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your support. Our customer is waiting for your reply.

    Should we refer only to the "Recommended Operating Conditions" for the voltage on each of the logic pins? In other words, regardless of the power domain used, can we refer only to R1.16 for GPIO3/4, R1.17 for GPIO5/6, and R1.13 for I2C and SPI pins and other GPIO pins?

    If my understanding is correct, GPIO3/4/5/6 can be pulled up as high as 5.5 V when configured as input, and I2C and SPI pins and other GPIO pins can be pulled up to the voltage of VIO_IN.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    My apologies on the late reply, you are correct with the fail safe the input voltage on these domains can be as high as 5V5, but the fail-safe. Now the fail-safe on the input buffer is tied to the input power requirement and due to the VIO_IN & VCCA being tied together this is not an issue.

    This is not an issue due to VCCA powering the device while simultaneously providing the input voltage at the above pins of concern, so there isn't a mode in which you will fail outside of recommended operating conditions, which is why typically for 3V3 input applications we ask customers to tie in VCCA & VIO_IN for simplicity.

    If 5V0 input is used, please follow the recommendations of the User's Guide for the PMIC TPS65931211 as there will be a change in the assumptions of the voltage since 5V0 is no longer a recommend voltage level for the VIO pin.

    Thank you for your patience.

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your reply.

    I am concerned about input 3.3V (VIO_IN) to IO pins that has input or output buffers using internal 1.8V LDO.

    GPIO3/4/5/6 that has input buffers of fail-safe should be able to be pulled up as high as 5.5 V when configured as input.

    Can 3.3V (VIO_IN) really be input to other IO pins that have input or output buffers using internal 1.8V LDO?

    If VCCA uses 5V and VIO_IN uses 3.3V, PVIN_LDOn will also use 3.3V as recommended in "3.1.2 Using 5V Input Supply" on the User's Guide.

    In that case, will the input voltage conditions for the IO pins using VIO or internal 1.8V LDO also change?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    Daisuke Maeda said:

    In that case, will the input voltage conditions for the IO pins using VIO or internal 1.8V LDO also change?

    I understand the concern especially looking at the block diagram, as you can see for the pins 3,4, 5, & 6 which use exclusively the internal LDOs for the sources of the 4 pins for both the input and output buffers. The architecture for the GPIOs are different, hence the different line items you pointed out in the specifications section.

    For all other GPIO pins the input and output buffers are split between LDOVINT and VIO_IN, the specifications are correct, 3V3 is allowable on the other GPIO pins, in this case input 3V3.

    The User's Guide outlines the pull up resistors needed and what domain to pull up to if clarity is needed.

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your reply. I’m sorry for asking the same thing repeatedly.

    Nicholas McNamara said:
    I understand the concern especially looking at the block diagram, as you can see for the pins 3,4, 5, & 6 which use exclusively the internal LDOs for the sources of the 4 pins for both the input and output buffers. The architecture for the GPIOs are different, hence the different line items you pointed out in the specifications section.

    As described in note (3) of the “Recommended Operating Conditions” GPIO3/4/5/6 can be pulled up as high as 5.5 V when configured as input, correct?

    And they can be pulled up to 5.5 V regardless of the voltage applied to VIO_IN, correct?

    "(3) The input buffer of a fail-safe GPIO pin is isolated from its input signal. Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V."

    Nicholas McNamara said:
    For all other GPIO pins the input and output buffers are split between LDOVINT and VIO_IN, the specifications are correct, 3V3 is allowable on the other GPIO pins, in this case input 3V3.

    Other IO pins can be pulled up to 3.3 V (VIO_IN) when configured as input, correct?

    Nicholas McNamara said:
    The User's Guide outlines the pull up resistors needed and what domain to pull up to if clarity is needed.

    I cannot find information about the needed pull‑up resistors in the user's guide.

    Figure 3‑2 shows the power domains corresponding to the direction settings, and most of them are 1.8 V. If this is correct, then most of the pins cannot be pulled up to 3.3 V, and the SK‑AM62A‑LP (PROC135A1) would be incorrect.

    Best regards,

    Daisuke

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your support. Our customer is waiting for your reply.

    Our customer is referring to SK-AM62A-LP for their custom board design using AM62A7 and TPS65931211-Q1, but VDDA uses 5V instead of 3.3V.
    Please clarify whether IO pins using VINT/VRTC (1.8V) can be pulled up to 3.3V (VIO_IN).

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    Daisuke Maeda said:

    And they can be pulled up to 5.5 V regardless of the voltage applied to VIO_IN, correct?

    "(3) The input buffer of a fail-safe GPIO pin is isolated from its input signal. Therefore, the input voltage to a fail-safe pin can be as high as 5.5 V."

    Only when power is applied to the VCCA pin, as the input buffer requires power to function, so this fail safe is only applicable when VCCA > VCCA_UVLO

    Only applies to the pins noted in (3), so yes that's correct with the exception above.

    Daisuke Maeda said:

    Other IO pins can be pulled up to 3.3 V (VIO_IN) when configured as input, correct?

    That is correct, from the recommended specifications for all other IO pins.

    Daisuke Maeda said:

    I cannot find information about the needed pull‑up resistors in the user's guide.

    Figure 3‑2 shows the power domains corresponding to the direction settings, and most of them are 1.8 V. If this is correct, then most of the pins cannot be pulled up to 3.3 V, and the SK‑AM62A‑LP (PROC135A1) would be incorrect.

    Please see the footnote below for the open drain signals.

    R1.13 in the specifications does point out that you can use up to VIO voltage for the input and output, so for the pull ups you can safely source from the VIO_IN rail. While I understand it shows that, again please follow the specifications, it makes note of the specific GPIOs where the voltage is allowed. Block diagrams are abstractions, but not exact, please when refer to specification line items over the block diagrams.

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Thank you for your reply.

    I understand the input voltage on each IO pin as follows.

    For nPWRON/ENABLE (input) pin, R1.18 in the "Recommended Operating Conditions" applies. Therefore, the pin can input up to 5.5 V (VVCCA).

    For nINT (open‑drain output) pin, "RECOMMENDED EXTERNAL PU/PD" in the "Table 6-2. Signal Descriptions" applies. Therefore, the pin can input up to 5.5 V (VVCCA).

    For GPIO3/4/5/6 pins, when configured as input or open‑drain output, Note (3) in the "Recommended Operating Conditions" applies. Therefore, the pins can be input as high as 5.5 V if VCCA > VCCA_UVLO.

    For nRSTOUT, I2C and SPI pins and other GPIO pins, when configured as input or open‑drain output, R1.13 in the "Recommended Operating Conditions" applies. Therefore, the pins can input up to 3.3 V (VVIO_IN).

    Our customer will refer to SK‑AM62A‑LP (PROC135A1) for pull-up on each IO pin.

    I would appreciate it if you could point out any errors in my understanding.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    Please, for some of these functions see the PMIC's User guide, I know you've been focused on the input voltage domain, but more than that each of these pins have certain functions that need to be timed correctly like for instance GPIO9 is a ENABLE for the VPP function that is runtime configurable and just having it pulled up may not provide the functionality you desire.

    Please follow the latest AM62A LP EVM, I'm looking at PROC135E2 which some of the features are tied to logic both from the board and the SoC/MCU connect them like so if there's an issue please say so, but you should know what voltage(s) you want on the core, ram, etc...

    I do see issues just tying all of the inputs to VCCA as the rising edge may not get capture at the correct moment by the PMIC's state machine. I will not look through every single tie to the GPIOs inputs as I don't know what you want in your design, again please look at the PROC135E2 for which GPIOs are tied to what logic.

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Guru 20305 points

    Hi Nicholas McNamara-san,

    Happy New Year. Thank you for your reply.

    The latest revision of the SK‑AM62A‑LP is PROC135A1, so we should refer to PROC135A1 (the design file below), not PROC135E2, right?

    SK-AM62A-LP Design File Package (ANF)

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Mastermind 22500 points

    Hello Daisuke,

    If that is in fact the latest, please go ahead with that revision of the board, my apologies with slower responses.

    If there is a major difference between the E2 vs A1 regarding PMIC connections, please do raise a question as you deserve answer, but as for as the IO and pull up connections I do not see and issue on the voltage levels.

    BR,

    Nicholas McNamara