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TPS650864: OTP programming in TPS6508640

santhosh m
Prodigy 40 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPS65086

Hi team,

We recently purchased the TPS6508640 to power the Xilinx Zynq Ultrascale+ ZU7–ZU15, as recommended in the datasheet.

In Table 4-1 (Default Values), the datasheet lists the default voltages provided by all regulators. Doesn't it means that PMIC outputs these voltages automatically after it powers on?

Because, we have to reconfigure the registers every time the system powers up, which seems incorrect since we expect the PMIC to output its default voltages on startup.

Is there any way to OTP-program for TPS6508640 so that our configured voltages are applied permanently at power-up? Or is there another process we should follow to make the PMIC automatically provide the desired voltages?

Best regards,

Santhosh

  • 0
    TI__Genius 13167 points

    Hi Santhosh, 

    Thank you for reaching out on E2E. 
    I assume this is related to your other thread about the same device. 

    TPS6508640 will come pre-programmed. This will power on to the pre-set values listed in the datasheet by default. 

    TPS650861 is a user-programmable version of the device from the same family, and this comes as a blank device. 

    Are you able to confirm the part number for me, by checking the top marking, and by reading the DEVICEID2 register (address 0x01)?

    The steps for saving an OTP program are listed in the NVM programming guide, but this requires a 7V source be temporarily applied on the CTL4 pin.
    https://www.ti.com/lit/ug/swcu188/swcu188.pdf


    If the TPS65086x device is already installed on your custom board and this is not possible, please double check the part number,
    since the TPS6508640 should be powering on to the desired voltage levels by default, without the need for an extra programming step. 

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Prodigy 40 points

    Hi,

    Thanks for the reply.

    Yes, I can confirm the part number. It is TPS6508640. In the DEVICEID2 register value is 00100100, which matches the TPS6508640.

    Before OTP programming, I need to clarify one thing about controlling the power rails. I have enabled all of the outputs using the i2c_rail_en registers. So are you saying that once the PMIC has supplied the enough voltage and current, the PMIC will output the default voltages in all outputs without any additional configurations?

  • +1 in reply to santhosh m
    TI__Genius 13167 points

    Hi Santhosh, 

    Thank you for confirming. 

    The TPSS6508640 power-up sequence is triggered once CTL3 pin is asserted HIGH (and for valid VSYS):

    Power sequence can be initiated this way, instead of manually enabling each regulator via I2C.

    Please refer to the TPS6508640 Design and Settings of the datasheet for more information. 

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Prodigy 40 points

    Hi Sarah,

    Yes, I have gone through the datasheet, but I’d like to explain what we expect from this IC. Our goal is to power all the required rails from a single input supply without any configuration after that.

    So i can understand that, we should provide power to VSYS pin and also an external control signals via the CTLx pins to configure the power outputs.

    Instead of powering the PMIC first and then HIGH and LOW CTLx pins to enable power rails, could I simply short the needed CTLx to 5V and feed power on Vsys pin? That way, after power-on there’s no need to control the switches again.

    Best Regards,

    Santhosh.

    (Note: Above is the actual answer to the question which was raised on this forum i have touched the other as a solution by mistake)

  • 0 in reply to santhosh m
    TI__Genius 13167 points

    Hi Santhosh, 

    Yes, VSYS needs to be supplied, and CTLx pins need to be controlled according to desired operation:

    CTL3 can be shorted HIGH, but I would not recommend shorting this to 5V. 
    The maximum recommended voltage should be 3.3V:

    Instead I would recommend tying this to the LDO3P3 output, so that this doesn't violate any timing or voltage specs.

    That way, the CTLx is automatically asserted after powering on VSYS, and no need for external CTL control.

    This would be fine for the power-up sequence,
    but please be aware that the normal TPS6508640 power-down sequence is typically initiated when CTL3 is asserted LOW.
    If VSYS is asserted LOW first, then device will follow Emergency Shutdown sequence instead. 

     Let me know if you have any further questions.

    Best Regards, 
    Sarah

  • 0 in reply to Sarah Lao
    Prodigy 40 points

    I have two questions regarding your suggestion:

    LDO3P3 appears to be enabled only when the CTL6 pin is in a high state, but this behavior is not mentioned anywhere in the datasheet. Also, when CTL6 is high, I see 0.9 V at the BUCK2 output, instead of this we need 0.85 V.

    You mentioned that powering off the VSYS pin directly would trigger an emergency shutdown instead of a proper power-down sequence. What exactly does this emergency shutdown do to the PMIC, and what are the potential consequences to an SOC (Xilinx Zynq UltraScale+ ZU7CG ±ZU15EG) which was powered by it?

  • 0 in reply to santhosh m
    TI__Genius 13167 points

    Hi Santhosh, 

    LDO3P3 should not be dependent on CTL6, it should automatically ramp up when VSYS ramps up:

    Is this also the case with LDO5P0 on your board? 

    CTL6 should only be affecting Buck2 voltage 0.85 -> 0.9V, it should not be gating the LDO3P3.

    Emergency Shutdown has all rails shut down 444 ns after VSYS goes below 5.4V:


    As for the potential consequences, this would be more of a question for the Xilinx processor, what happens if the recommended power-down sequence is violated.

    From AMD forums regarding Ultrascale+ power sequence: 

    Best Regards, 
    Sarah