Part Number: BQ25188
Power Dissipation
The BQ2518x is a linear charger with power path. Power path is a feature that allows the BQ2518x to power the system from the input source while simultaneously charging the battery. The back-to-back input FETs (Q1/Q2) regulate the SYS pin to the target system voltage. The BATFET (Q3) regulates the charge current to the battery during the constant current (CC) charging phase and regulates the BAT pin to the target battery regulation voltage during the constant voltage (CV) phase.
During charging, power is dissipated by both the input FETs and the BATFET. The total power dissipated by the device is therefore the sum of these two contributions:
PDISS = PSYS + PBAT
Where
PSYS = (VIN - VSYS) * IIN ...input FETs
IIN = ISYS + IBAT
PBAT = (VSYS - VBAT) * IBAT ...BATFET
Combining terms gives the total power dissipation:
PDISS = [(VIN - VSYS) * (ISYS + IBAT)] + [(VSYS - VBAT) * IBAT]
An estimate of the die junction temperature can be obtained from
TJ = TA + θJA * PDISS
The thermal resistance θJA is provided in the BQ2518x datasheet, and ambient temperature is typically assumed to be 25°C. Because θJA is strongly dependent on PCB layout, this calculation should be regarded as an approximation rather than an exact result.
Efficiency
The efficiency, denoted by η, is defined as the ratio of output power to input power. For the BQ2518x, efficiency can be expressed as
η = 1 - (PDISS / PIN)
Since the output power is related to input power by
POUT = PIN - PDISS
Efficiency may also be written as
η = (PIN - PDISS) / PIN
Minimizing power dissipation in the BQ2518x
To minimize power dissipation in the BQ2518x, the voltage drops across the input FETs and the BATFET must be minimized. One effective approach is to operate the charger in pass-through mode and use an MCU to dynamically adjust the input voltage to the minimum level required for charging. Under this approach, the minimum SYS voltage (effectively the input voltage in pass-through mode) is limited by dropout and sleep mode.
In pass-through mode, the input FETs are fully enhanced, and the SYS voltage is given by
VSYS = VIN - IIN * RDS(on)
Thus, VSYS is approximately equal to VIN.
The power dissipated by the input FETs in pass-through mode is
PSYS = IIN2 * RDS(on)
The minimum SYS voltage required for charging depends on both the charge current and the associated dropout voltages. For example, consider a charge current of 1A using worst-case RDS(on) values of 470mOhm for the input FETs and 90mOhm for the BATFET of the BQ25188. Under these conditions, the input FET dropout voltage is 470mV and the BATFET dropout voltage is 90mV.
For a battery voltage of 3.6V:
VSYS(min) = 3.6V + 0.09V = 3.69V
VIN(min) = 3.69V + 0.47V = 4.16V
This results in VIN - VBAT = 560mV, which is above the sleep mode threshold. In this case, dropout is the limiting factor.
If the charge current is reduced to 100mA, the dropout voltages scale proportionally:
Input FET dropout = 47mV
BATFET dropout = 9mV
The minimum voltages become:
VSYS(min) = 3.6V + 0.009V = 3.609V
VIN(min) = 3.609V + 0.047V = 3.656V
Here, VIN - VBAT = 56mV, which is below the sleep mode threshold. In this case, sleep mode is the limiting factor rather than dropout.
When operating with this approach, VINDPM and VDPPM should be disabled.