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TPS6594-Q1: Can't power on with SK-AM69

Jeff YANG
Mastermind 8570 points

Part Number: TPS6594-Q1
Other Parts Discussed in Thread: SK-AM69, , AM69

Hi,

We follow the SK-AM69 EVM to design the TPS6594-Q1, but can't bring up.

We have confirmed that the PMIC VINT and VRTC outputs are both at 1.8 V.

According to the specification, BUCK3 should be enabled first. However, based on our measurements, we observed that after several PWM retries, it stops switching. The same behavior is seen on the other BUCKs and LDOs as well.

Our questions are as follows:

  1. Is there any tool available to read out the PMIC status or registers?

  2. When this PMIC is used with the AM69, is firmware programming required?

  3. Is there any pin that can be used to confirm whether the PMIC is in a retry state?

  4. Does the 32.768 kHz OSC affect the PMIC operation?

Thanks!

Jeff

  • 0
    TI__Mastermind 22770 points

    Hello Jeff,

    See the User's guide for the PMIC part (click here)

    1)

    You can use any I2C reader tool, I mean even an arduino can be used to perform a register readback on the device.

    The only issue I can forsee is that the pull registers need to be placed to a valid voltage source and VIO (PMIC pin) needs to be powered.

    Typically the pull ups are sourced off of the PMIC, and the VIO is tied to the input of the PMIC (VCCA Pin on the PMIC) if the input source is 3V3.

    You want to read registers 0x5A to 0x6C on I2C address: 0x48

    Jeff YANG said:

    • When this PMIC is used with the AM69, is firmware programming required?

    No, there is no additional firmware programming required for the PMIC, it should be noted that the part to be used with AM69 is TPS6594133A, revision 5 is the latest firmware version.

    Jeff YANG said:

    • Is there any pin that can be used to confirm whether the PMIC is in a retry state?

    No explicit pin, but a good pin to see if the power up sequence even begins is the GPIO9, which turns on the VDD_IO supplies.

    After 15 toggle attempts the PMIC will no longer respond for any power up sequences since the recovery counter has been saturated, more in the datasheet on this function.

    Jeff YANG said:

    1. Does the 32.768 kHz OSC affect the PMIC operation?

    No, it does not, having the pin 38, 39, & 40 populated with the crystal and loading caps will provide the extra RTC functionality, but it is not needed for function on the power up sequence.

    Trouble shooting

    Now for my recommendation on what to look for, work through the power sequence and see where it stops on the bring up.

    If all signals go up, rails and IO with nRSTOUT being the last, but then goes down immediately and this pattern repeats for 15 attempts, then I would look at GPIO8 & GPIO10, these need to be up by the end of the sequence when nRSTOUT is released.

    These pins monitor the peripherals that the PMIC attaches to through voltage monitors and status pins back to the PMIC's GPIOs (8 & 10)

    If you still need help after the above recommendation, then you can provide a scope capture of the following:

    1. GPIO9 (Trigger off of this or if doesn't go high ENABLE pin)

    2. GPIO8

    3. GPIO10

    4. nRSTOUT

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Mastermind 8570 points

    Hi Nicholas,

    it should be noted that the part to be used with AM69 is TPS6594133A, revision 5 is the latest firmware version.

    => How do we know the  TPS6594133A is revision 5? IC makring can identify it? 

    Thanks!

    Jeff

  • 0 in reply to Jeff YANG
    Mastermind 8570 points

    Hi Nicholas,

    1. We can read register 0x48 as shown below.

    Register readback comparison:
    ⇒ DUT1 (DUT2)
    5A ⇒ BA (BB)
    5B ⇒ 00 (02)
    5D ⇒ 00 (08)
    5F ⇒ 01 (01)
    60 ⇒ 04 (04)
    65 ⇒ 02 (02)
    66 ⇒ 01 (01)
    67 ⇒ 08 (0A)
    69 ⇒ 06 (06)
    All other registers are 0x00.

    Hardware difference:
    DUT1 has the bead between the BUCK output and the AM69 removed.
    DUT2 is normally connected to the AM69.

    2. How can we confirm that the TPS6594133A is revision 5?

    3. GPIO9 retries 15 times, as shown in the waveform below.

    CH1:VCCA

    CH2:EN

    CH3:GPIO9

    CH4:BUCK3

    CH1:VCCA

    CH2:EN

    CH3:GPIO9

    CH4:LDO1

    Thanks!

    Jeff

  • 0 in reply to Jeff YANG
    Mastermind 8570 points

    Hi Nicholas,

    We have read [3h]=05, is it mean revision 5? thanks!

    Jeff

  • 0 in reply to Jeff YANG
    Mastermind 8570 points

    Hi Nicolas,

    Would you give us suggestion since it is urgent? thanks!

    Jeff

  • 0 in reply to Jeff YANG
    TI__Mastermind 22770 points

    Hello Jeff,

    That's great, but what I needed was the captured I ask, the registers are useful still.

    https://www.ti.com/lit/ug/slvuci2a/slvuci2a.pdf?ts=1766412097875&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS6594-Q1

    Please look at the section titled: 5.2 PFSM Triggers & 5.3 Power Sequences

    Work through the power sequence and see if there's anything wrong with the resources flagged.

    This will give you something to look at, the GPIO10 & GPIO8 are signals that need to stay up at the correct times, which DUT looks like it may not be getting such a thing, have you confirmed that because that scope capture doesn't have the GPIO10 or GPIO8 on it.

    When you do have this repeated 15 attempts pattern, please have a more detailed or zoomed capture as it is hard to make out the differences in timing as this is a systematic error.

    DUT1, look at GPIO 8 & GPIO 10, are they up after nRSTOUT goes high?

    DUT2, Look at the interrupts and take a detailed scope capture (not a zoomed out one), of the affected LDOs / BUCK regulators

    BR,

    Nicholas McNamara

  • 0 in reply to Nicholas McNamara
    Mastermind 8570 points

    Hi Nicholas,

    Got it, we are check for the  GPIO 8 & GPIO 10 and the  interrupts. Will provide later.

    And we want to check TI EVM NVM code have impact for the issue? thanks!

    Offset

    Our MB

    TI

    1h

    82

    82

    2h

    3A

    3A

    3h

    05

    03

    Jeff

  • 0 in reply to Jeff YANG
    TI__Guru 52771 points

    Hi Jeff,

      Thank you for reaching out with your PMIC questions. The expert for the PMIC device is out-of-office until next Monday, so please expect a response regarding this question early next week. Thank you for your patience.

    Thanks!

    Phil

  • 0 in reply to Phil Yi
    Mastermind 8570 points

    Hi Nicholas,

    Update the waveform.

    DUT1, look at GPIO 8 & GPIO 10, are they up after nRSTOUT goes high?

    => GPIO8 rises to 3.3 V along with PU VCCA.
    nRSTOUT remains low.
    GPIO10 remains low.

    GPIO8 rises to 3.3 V along with PU VCCA.
    GPIO9 toggles high and low 15 times.
    GPIO10 remains low.

    DUT2, Look at the interrupts and take a detailed scope capture (not a zoomed out one), of the affected LDOs / BUCK regulators

    => Confirmed that the earliest power rails to shut down are LDO3, BUCK3, and BUCK1/2. All power rails output the correct voltages before shutting down. This sequence repeats 15 times.

    LDO3

    BUCK3 and BUCK1/2

    And is possible we provide the customer board to you to help us check the fail symptom?

    Thanks!

    Jeff

  • 0 in reply to Jeff YANG
    Mastermind 8570 points

    Hi Nicholas,

    May I have your comment for above issue? thanks!

    Jeff

  • 0 in reply to Jeff YANG
    TI__Mastermind 22770 points

    Hello Jeff,

    My comments are on the following, but you need to look at the interrupts and investigate further based upon that.

    DUT1, the interrupts indicate LDO1 to be an issue, that and the nRSTOUT never goes high at any point in powerup indicating there's a problem sometime between start up and expected failure, verify the last known good regulator, and then see the regulators after that point in time. See the User's Guide I had posted earlier in the thread.

    GPIO10 is used as signal for external voltage monitors, this is shown in the User's Guide.


    DUT2, again look at the interrupts and try to correlate the issues. Please read the User's Guide and tell me which part is difficult to understand when trouble shooting.

    Jeff YANG said:

    And is possible we provide the customer board to you to help us check the fail symptom?

    Please reach out to your local Field Applications Engineer for additional assistance.

    Jeff YANG said:

    Got it, we are check for the  GPIO 8 & GPIO 10 and the  interrupts. Will provide later.

    And we want to check TI EVM NVM code have impact for the issue? thanks!

    The issue that you're currently experience has nothing to do with the quality improvements made within in the revisions, the sequences are the same, so the issues would be similar whether it's revision 3 or 5, but all orderable parts at this moment are/will be revision 5.

    BR,

    Nicholas McNamara