Part Number: LM5050-1

Hi, 

I am using the LM5050-1 as it is depicted in the setup below:

Setup

Figure 1 Or-ing Test Setup

The PSU is linear 350W PSU.

The load are high power resistors.

Waveforms

Figure 2 3.5V Output voltage 0-A

Figure 2 depicts the Vgs voltage generated by the LM5050-1 with 0A flowing through the OR-ing FET.

Figure 3 3.5V Output Voltage 0A negative spike zoom

As we see in Figure 2 and more clearly in Figure 3 the Vgs voltage generated by the LM5050-1 drops down to 0V with an inconsistent pattern of negative spikes.

Figure 4 3.5V Output Voltage 0-4.5-12.5 A Step Load

Figure 4 depicts the generated Vgs voltage by the LM5050-1 in relation to the output load current flowing through the OR-ing FET. The Vgs voltage turns the OR-ng FET full on and fails to regulate his output voltage to 22mV as stated in the LM5050-1 datasheet.

Figure 5 6V Output Voltage 0A

In Figure 5 we increased the voltage of the linear PSU from 3.5V to 6V. The behavior of the LM5050-1 changed regarding of the generated Vgs voltage. No the LM5050-1 sets the Vgs voltage in a level capable of regulate the Vds voltage of the Or-ing FET to 22mV even without the existence of an output load current.

Figure 6  6V Output Voltage  0-4.5-6A Load Step

Next, we increased the load’s current from 0A to 4.5A and then to 12A, leaving the output voltage of the Linear PSU to 6V. The generated Vgs voltage of the LM5050-1 increased to specific stages in order to regulate the Vds voltage to 22mV.

Conclusions

As you see in waveforms 2-to-4, LM5050-1 fail to regulate the Vgs Voltage of the OR-ing FET in order to regulate his Vds voltage to 22mV. Instead it turns the OR-ing FET full on regardless of the load’s current. Furthermore there are some random negative spikes on the Vgs voltage which drive the Vgs voltage from full on to full of. Those spikes are random and can’t be correlated with a specific frequency of the system. The PSU we used was linear and the load was high watt resistors. The output voltage of our PSU had been set to 3.5V.

When we increased the output voltage of our linear PSU from 3.5V to 6V keeping the same setup as Figure 1 we took the waveforms 5 and 6. As you see when there is no load current the VGS voltage of the OR-ing FET regulates the VDS voltage on 22mV. Furthermore the negative spikes also vanished. Next, we increased the current from 0 to 4.5 and then to 12.5V. As you see the LM5050-1 changed the VGS voltage of the OR-ing FET in order the regulate his Vds voltage in relation to the load’s current.

We will appreciate your guidance with the below requests:

1. Please verify that the correct behavior of the LM5050-1 controller is the one we observed in waveforms 5 and 6 with the Linear PSU’s output set in 6V.
2. Please verify that the LM5050-1, taken that is supplied from a external 12V source, can work as an OR-ing FET controller in a range of output voltage from 3.5-to-18V and a range of load currents of 0-50A.
3. If the second statement stands correct, we would need your advice to:
   1. Enlighten us why the behavior of the LM5050-1 changes with the output voltage of the Linear PSU.
   2. Give us any recommendations on how we can overcome this issue.

Lastly, I want to inform you that this was only a test board which has been created to map the operation of the LM5050-1 in all the range of the possible output voltages and currents of our application. At the end product the Linera PSU will be replaced with an isolated switching power supply. The operation of the LM5050-1 in a relatively low noise environment creates inconsistencies on how the Or-ing FET is controlled in relation to the PSU’s output voltage. If in those inconsistences will be added the switching noise of the full bridge rectifier of the isolated PSU, wouldn’t we expect more inconsistent behavior by the LM5050-1?  

Kind regards