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UCC5350: Design Questions of SiC FET in Parallel

Francis Jiang
Expert 4140 points

Part Number: UCC5350

Hi Team,

Customer used UCC5350 as SiC gate driver, and has below questions, could you please help provide your professional advices? Thanks in advance.

1. What are the peripheral circuit and layout recommendations for driving dual parallel SiC FETs? Do the clamp pins also need separate split resistors connected to the gates of different MOSFETs?

2. In high-current hard-switching: what are the recommended design considerations for driving dual parallel SiC FETs? Should the driving of the two FETs be independent, or should one driver IC drive both parallel MOSFETs?

3. In the diagram below, when evaluating peak current, should the internal resistance of the MOSFETs in this dual parallel FETs configuration be divided by 2?

image.png

BRs,

Francis

  • +1
    TI__Expert 4075 points

    Hi Francis,

    1. Feel free to read up on these E2E threads that should help to answer your question about driving MOSFETs in parallel with UCC5350MC: [Link 1] [Link 2]

    2. In high-current hard-switching, it may be beneficial to use two independent ICs so that each FET has its own output and clamp pins in order to be able to handle potential transients caused by high-current hard-switching.

    3. I believe for R_GFET_Int, you would need to multiply it by 2 since there would be two gate resistances that make up the total resistance, along with two resistors each for R_GON and R_GOFF. Additionally, R_NMOS, R_OH, and R_OL would not need to be multiplied by 2, since these resistances are internal to the gate driver.

    Best regards,

    Will