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Original question:

LM5146: LM5146 with LMG2100R026

LM5146: Oscillation in VGS

Frank Cai
Intellectual 1935 points

Part Number: LM5146
Other Parts Discussed in Thread: LM70860

Hi Team,

Customer is evaluating LM5146 and they saw some osillation on both high-side MOSFET VGS and low-side MOSFET VGS during the deadzone time, I am wondering:

  1. Do you see similar osillation in EVM by the same operating condtions? Vin=48V, Vout=8.5V, Iout=5A, Fsw=250kHz. 
  2. To mitigate the osillation, snubber circuit is the best choice, right? Do you have another suggestion?
  3. Are there any risk for this kind of osillation?

image.png

BRs.

Frank Cai

  • 0
    TI__Mastermind 23702 points

    Hello Frank

    This could be due the way customer is probing the signal. Let's make sure we are using shortest loop method. Also incorporate pigtail probing in measurement. Kindly share schematic and layout as well. 

    Thank you

    Regards 

    Onkar Bhakare 

  • 0 in reply to Onkar Bhakare
    TI__Guru* 82817 points

    Hi Frank, 

    Just to add what Onkar mentioned. This is capacitive coupling from the SW voltage, with a subsequent resonance created by the parasitic gate loop inductance. What's helpful here is to keep the LO trace short and wide over a GND plane.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Intellectual 1935 points

    Hi Tim, Onkar,

    Thanks for the comments.

    It seems that the LO trace is too long in this case, beside the PCB layout, do you have any comments for the schematic? The attachment is their schematic.

    SCH_powerSupply_V4.3_Only_TI.pdf

    Currently they use LM5146 and they saw thermal issue, running the device about 5mins, the IC temperature raised to about 110C when ambient temp is about 14C. LM5146 doesn't look good in their application and I am wondering if the layout will cause the thermal issue in this case. The operating conditions is Vin=48V, Vout=8.5V, Iout=5A, fsw=250kHz.

    Could you please check on the EVM for following questions:

    1. Please get the waveform for both high-side and low-side VGS, so that customer can take it as reference.

    2. Could you try the same operating conditions and see if there are any thermal issue?

    3. Could we have a call together with customer to check their layout if needed?

    BRs.

    Frank Cai

  • 0 in reply to Frank Cai
    TI__Guru* 82817 points

    Hi Frank,

    Connect VOUT to VCC through a diode to provide bias power to VCC. This will reduce the IC operating temperature. In terms of the gate drive, remove the series resistors and diode on the low-side gate - these just add parasitic inductance and are not recommended (see data sheet and EVM schematics). They're also not needed on the high side, as the boot cap series resistor can manage the turn on. Remove the caps around the low-side FET as well, as these just increase losses. What are the FET part numbers?

    Go ahead and complete the LM5146 quickstart calculator for this design – we can have a call to review everything if needed. Note that if Iout = 5A, we recommend a converter for this...LM70860 80V/6A for example...much easier solution.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Intellectual 1935 points

    Hi Tim,

    Understood your point, I am now letting them to input in the calculator.

    Besides, for the PCB layout, I saw there are some guide in the datasheet, but it is mainly on gate driver trace, do you have some other suggestion on parasitic parameter limitation? We can understand the shorter and the smaller the trace would be good for layout, customer is wondering if we can provide some parasitic value and they can take it into PCB layout reference.

    BRs.

    Frank

  • 0 in reply to Frank Cai
    TI__Guru* 82817 points

    Hi Frank,

    Target is < 10nH of parastic inductance. Take the waveform as well with the SW voltage, so we can see if it's capacitive or inductive related.

    Regards,

    Tim