TPS7A8300: Why did TPS7A8300 output 2V when it work at 3.3V adjustable mode and EN is pull down?

Part Number: TPS7A8300

Hi,

On my board, There are two TPS7A8300s which output 3.3V and 5V separately. They all work at adjustable mode through external resistor divider at FB PIN, and have the same pcb layout design. Their EN pin are connected to MCU, and also pull down with 10K resistor. After power on and before MCU drive high to EN pin, EN should be pull down and two TPS7A8300s couldn't output voltage. But the TPS7A8300 for 3.3V output 2V at this time slot, then output 3.3V after EN is drived high by MCU. The TPS7A8300 for 5V is work normally which could ramp up from 0V to 5V directly after EN is drived high by MCU . For excluding the impact of MCU, I use anohter board which don't programm firmware of MCU yet. That means all PIN of MCU will be in the floating state and EN PIN should always be pull down.  After power on, I get fixed 2V by using multimeter for 3.3V TPS7A8300. 

Why this TPS7A8300 on my board have 2V output during EN pin pull down? Could you please verify this problem on your demo board?

Thanks in advance!

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                                                     Figure1.  TPS7A8300 for 3.3V

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                                                                Figure2.  TPS7A8300 for 5V

 

Best regards!

Jason 

 

 

 

 

 

 

 

  • Hey Jason,

    Can you please provide a scope shot with VIN, VEN and VOUT during this behavior?

    Thanks,

    Vahnroy

  • Hi, Vahnroy:

    Thanks!

    Please see below scope shot with VIN 5V5, VEN and VOUT 3.3V. You can see that VOUT source 2V before EN is driven high. 

    I also get a strange slot marked orange which VIN is behind VOUT. It violate causality

    Is there other source inserting into 3V3 rail before VIN 5V5 start up?

    Best regards!

    Jason 

  • Hey Shen,

    It appears another source is pulling up the output. Is there anyway you can isolate the LDO from the rest of the system?

    Thanks,

    Vahnroy

  • Hi, Vahnroy:

    There are only two source rail ahead of VOUT 3.3V, those are MCU_3.3V and VIN 5.5V( this 5.5V is VIN shown above scope shot). The sequence between MCU_3.3V and VOUT 3.3V is  shown in below figure. Then I disable MCU_3.3V through pull down EN pin of buck which source MCU_3.3V. So, the MCU will not be power on. EN PIN of TPS7A8300  always be pull down. But, I get fixed 2V by using multimeter. 

    why?

    Best regards!

    Jason

  • Hey Jason,

    Is this behavior being seen across multiple devices?

    If not can you try an ABA swap. Swapping the device for a new device and seeing if the problem persists.

    Thanks,

    Vahnroy

  • Hi, Vahnroy:

    I try another board, also has the same issue. This issue only happen on VOUT 3.3V, but VOUT 5V which another TPS7A8300 on the same board could ramp up from 0V to 5V normally after EN is driven high. So I ask for you that hope you can try the same setup on demo board. Please note that must keep EN low, and run at 3.3V adjustable mode, then to see if the 2V  appear on the VOUT of TPS7A8300 possibly. 

    Thanks in advance!

    Best regards!

    Jason

  • Hey Shen,

    Since this seems like a system level problem testing on our EVM won't be representative of your system. Due to the nature of LDO's the output cannot be high before the input.

    In order to confirm that this is not the LDO can you desolder the device and see if the voltage still appears?

    Thanks,

    Vahnroy

  • Hi, Vahnroy:

    I found root cause: a reference source(2.5V) insert or crosstalk into the VOUT 3.3V power plane in the ADC chip. When I cut off the 2.5V reference, 2V on the VOUT 3.3V disappear. So, there is sequence requirement between the VOUT 3.3V and  2.5V reference actually, but the datasheet don't mention this requirement. Ok, I will power VOUT 3.3V firstly then 2.5V reference.

    But I have another question as below figure shown:

    when I remove bead FB27 to cut off the input power to TPS7A8300, 2V on the VOUT 3.3V from reference source(2.5V) will flow to input of LDO reversely?

    I can measure this fixed 1.6V on the input of LDO. This kind of reverse flow come through the body diode of NMOS in the LDO?

    Thanks in advance!

    Best regards!

    Jason

  • Hey Shen,

    The output of the LDO should not be more than 0.3V above VIN as per the absolute maximum ratings section of the datasheet

    Yes, the 1.6V is caused by reverse current across the body diode of the pass fet.

    Thanks,

    Vahnroy