Part Number: BQ34Z100-R2
Other Parts Discussed in Thread: BQ34Z100EVM, BQ34Z100, , EV2400, BQSTUDIO
Hi,
i've got some questions about learning cycle. We mostly have a problem with SoC percentage being a bit strange either close to 0% or 100%. We use 7s10p packet, cells are Samsung INR18650-35E, which are included as Ti Defined chemistries. Also we use bq34z100evm. Sadly logs for 2nd,attempt charging were lost.
Our settings for the package are included in .gg file. And I also add some logs.
Power supply: 29.5V, 2.2A
I'll start with a few offtopic questions which may be correlated to the problem above.
What's the formula for design energy? Is it Pack_capacity*single_cell_nominal_voltage = 33500*3.7V? We've used different one for 1st attempt.
Should we somehow reset the device if we want to perform another learning cycle - does previous learning cycle influence the next learning cycle?
Can we create a golden image on evm with different voltage divider settings, and then use it on custom pcb, which has different voltage divider? Is it possible to change divider settings after learning cycle is done?
For now we did 1 complete learning cycle, and the 2nd one is ongoing.
1st - Learning cycle FC is not equal -1
Here we had a problem where SoC hits 0% too quickly. And remaining capacity at 100% seems too low. As we can see for discharing2, remaining capacity is only 15940, we multiply it by 2, and its around 32k, should be 33500 atleast if we are correct. Its about 3.4V/cell when SoC hits 0% - should be about 3V. It can be seen clearly in Discharging2.log (2nd discharging of 1st learningcycle)
2nd- Learning cycle FC is equal -1
In this case, we set FC to -1, as we've thought may be using taper settings will lead as closer to SoC being correct. Sadly it is not. We've just performed charging, and we hit 100% of SoC when charger still applies current equal to 2.2A - shouldn't it hit 100% when current supplied is equal to taper current? Also for this try, we've used design energy formula mentioned before( pack_capacity * cell_nominal_voltage). Does design energy actually impacts learning cycle/soc readings?
The final question: We suppose, there is something wrong with our settings. What is it? We want to achieve 0% at about 3V/cell and 100% at about 4.12V/cell.
DataMemory_2nd.csv
DataMemory.gg.csv
Discharging2.log
