UCC256304: hiccup after spurious sudden stop of power conversion

Part Number: UCC256304

A customer has reached to us with spurious, but severe problems with their LLC application, (designed some years ago) with variable load scenarios.

The attached oscillogram (for full trace names: see its bottom part) shows a permanent hiccup condition, after very spurious events where the device enters (restart) hiccup behaviour. The device can be restarted correctly only after power cycling.

Apart from the potential cause of anomalies that stops the power conversion, the hiccup does not follow the 1 second pause constraint as outlined in datasheet and other papers. 

Actually, the hiccup rate goes at approx. a repetitive period time of 380 ms.

Regarding the signals shown here: noise peaks on Vcc (yellow) and VCR (green) represent mere pickup of fast slopes of the PFC switching amplitude.

It is curious that VCR does not have its continuous basic DC level that is normally approx. 3,0 V. In a power-up scenario, VCR jumps from 0 to 3 V in approx. 50 µs after Vcc has exceeded approx. 8 V. With some delay until RVcc has becom 12 V, the full waveforms are generated, hence with power conversion active.

Second curiosity: gate of lower MOSFET is high over the full time that RVcc is active.

To me it seems that the residual supply voltages across this hiccup cycling does not get low enough to accomplish a POR event.

Further information (measured on the fly):

  • FB voltage steady state approx. 8 V
  • LL/SS ramps up to approx. 5 V as soon as RVcc is active, however like simple RC-timing, not linear

Additional information: spikes from switching events seen over a few seconds in an oscillogram (with 15 MSPS) appear to increase clearly upon lower power output, when burst mode is active. Upon zooming in, high-level spikes appear to occur only in burst mode, upon burst start.

But during normal operation where these (narrow) spikes can be seen on ISNS, operation is not affected. That shows that the failure trigger points for the three types of OCP failure seems robust enough, not to flag a failure.

Having said that, no design modification to use the newer UCC25640x seems necessary. Moreover, the transformer is designed to meet the recommended dV/dt of approx. 4 V/ns.

ucc256304_capture_hiccup.png

  • Hi,

    Can you please tell which channel of scope is capturing which voltage?

    Regards,

    Sougata

  • I have edited the post, and now set the words that point to the bottom part of the oscillogram in blue bold type.

    Note regarding the 1 second hiccup interval according to datasheet: It might not work in this case, because the hiccup is associated with UVLO on RVcc. Any sort of timer could be disfunctional under this circumstance. But on the other hand: failure types that cause the controller to stop power conversion would always suffer of not operate restart attempts at this minimum period.

    But... when I compare the Vcc-capacitor on the EVM with the one in the customer circuit: EVM: 120 µF; customer circuit: 68 µF. This does not explain the missing 1 seconds, because a double value would result in approx. 750 ms period time.

  • Hi,

    I will get back to you . Can you please give me scope shot where you are seeing 1 sec hickup and mark it out in the scope shot.

    Regards,

    Sougata

  • Thanks for asking this - because the associated experiment shows that an extra judge opportunity is given!

    In order to try it out, I shorted the output. Indeed, the interval time is approx. 1 sec. (1.07-1.10 sec):    --- text continued below ---

    It becomes apparent that the Vcc-voltage is decreasing much slower, probably because of the internally driven disconnect of RVcc from its supply source Vcc and not because of UVlow. Anyway, the lower MOSFET on state in the fast hiccup scenario as shown a few days ago, perhaps associated with a 0V level on VCR might also contribute to quicker depletion of the Vcc buffer capacitor.

    Finally, the datasheet related hiccup timing only applies when no UVlo-event at RVcc occurs, while the associated timing circuitry must be supplied not by Rvcc but by Vcc. 

  • Hi,

    Can you please share design calculator and schematic ?

    Regards,

    Sougata

  • The customer has approved to share schematic (and of course calculator sheet), preferably using private message (hence, a friendship request has been made)

  • Hi,

    I have accepted the friend request.

    Regards,

    Sougata

  • Just as a matter of checking things: a week ago, a message containing schematic sheet was sent.

  • Hi Rob,

    I will get back you ASAP. 

    Regards,

    Sougata

  • Hi Rob, 

    Can you please share the testing condition at which you are seeing the problem? What is input voltage and load condition?

    Can you please share a scope shot where LO, SW node, ISNS waveform can be seen?

    Regards,

    Sougata

  • Input voltage before PFC is 230V AC, while for testing, load is programmed to vary between 0 and approx. 25 W. Which is normal maximum load. Further information is underway separately.

  • Hi,

    Understood. We will continue in chat. 

    Regards,

    Sougata

  • Apart from the private discussion related to schematic, It would be helpful if TI could confirm whether a hiccup as presented in the first oscillogram in the first thread posting is technically possible according to internal controller architecture (including the LO gate high) or not. This includes the apparent behaviour to not follow the > 1 sec hiccup rate as well as doing a normal restart after power cycling.

    BTW: in contrast to e.g. MCU systems, you cannot debug resp. trace which precise error is responsible for e.g. a 1 sec. hiccup according to datasheet. A specific fault isn't flagged for introspection anyway. Of course I don't expect that, but it makes failure analysis more difficult. In the block diagram and the table under chapter 7.4.3 I see approx. 12 possible fault causes. Table 2 isn't bad, but still not informative enough.

  • Hi,

    <1sec hickup rate is is highly impossible except 1 possibility that is at very low load, ISNS has lot of noise which may give false ZCS Flag. 

    Can you please share the screenshots of 12 possible faults here? I cant see any table like that in the datasheet.

    Regards,

    Sougata

  • twelve inputs according to this table:

    Less than 1 sec hiccup highly impossible... Thanks for confirmation, especially because of the association with low power levels: indications up to now seem to support that. Since you do not write "completely impossible". Nevertheless: the oscillogram on top of this thread proves that it can occur. I'd regard it a bit more as probable now that ISNS could be exposed to heavy noise bursts from whatever source - let's say from solar flares. ;-)

    The injection of repetitive narrow pulses of approx. +1.5V onto ISNS at a rate of 10 kHz (that was tested) could be insufficient to trigger ZCS fault.

    Question: How can I intentionally trigger a "regular" 1.1 seconds hiccup? This could help me to better analyse what's going on. And can you tell if such a hiccup as documented occurs with uninterrupted presence of 12V on RVcc? Or with an interrupted RVcc-presence as shown in the oscillogram on top of this thread?

    EDIT: I remember to have triggered a regular hiccup upon short circuit on the output (a few weeks ago), while its removal facilitated normal start without power cycling.

  • Hi,

    I am not seeing anything at <1sec fault hiccup except ZCS trigger. 

    If you want to hit regular 1.1 sec hiccup, then you may need to hit OCP faults by increasing the load current. 

    Regards,

    Sougata