Hello Jacob,

Thanks for the detailed failure description and attachments.

If the IC is burning, the most likely root cause is that at least on of the pins voltages goes outside the specification and the internal circuit takes damage due to electrical overstress (EOS).

At VIN up to 29V and VOUT of 26V, there a good margin to the abs max of VIN pin (40V) and SW pin (60V).
However, there is still a risk of negative undershoots. Here, the SW limit is give as -0.6V general and -2V for 10ns transients.

You have already shared a SW waveform measurement, but would it be possible to run another test and zoom in on the timescale to clearly see the undershoot length and amlitude?
In the waveform, it looks like there is some undershoot and oscillation at the moment the low side MOSFET turns on. (approx. -4V undershoot?)
You can also run this measurement with the resistive load to avoid damaging further ICs. This would also give a direct comparison on whether the undershoots change with a different load setup.

Gate resistances and snubbers are generally a good solution to reduce such overshoots, but if there are no footprints for these components and wiring needs to be added (like in your video setup), there is risk of noise coupling into the signals, potentially leading to even worse overshoots.

Best regards,
Niklas

Hello Niklas,

Thank you very much for the quick reply! Your analysis regarding the SW pin undershoots sounds reasonable. We plan to perform the requested measurements with increased time resolution tomorrow and share the results.

However, I still have some questions that remain unclear to me:

1. Gate Resistors Already Implemented: We already added 10 Ω gate resistors to both MOSFETs (as shown in the video), which noticeably improved the ringing on the SW pin. Despite this improvement, the IC still failed when increasing Vin to the level of Vout or above.

2. Why Does Failure Only Occur at Vin ≥ Vout? If the undershoots are the root cause, why does the IC only fail at the specific point where Vin ≥ Vout? The undershoots are present at all input voltage levels, so shouldn't the IC be damaged at lower input voltages as well?

3. Why Does Failure Only Occur with the Fan Load? We tested extensively with a 4 A resistive load, and the IC operates without any issues—even when Vin exceeds Vout. What characteristic of the fan load (inductive behavior, inrush current, back-EMF, etc.) could explain why the failure only occurs with the fans connected?

We appreciate your support and look forward to your thoughts on these points.

Best regards, Jacob

Hello Jacob,

Thanks for the additional information.
1. So additional gate resistance already brought an improvement, but the failure still persisted. This would mean the worst case ringing is still to strong, even with the improvements of the gate resistance.

2. I do not have an explanation for this yet.
The TPS43061 device does not have a "bypass mode", where it turns on the high side MOSFET 100% for VIN > VOUT. This means the MOSFET can quickly break if there is a load due to overstress on the body diode. For prevention of this, your design already has an additional diode in parallel to share the current, which is good.
In short, the TPS43061 should not switch while VIN > VOUT and there can be no SW under-/overshoots.
However, I do not know how the switch node behaves in the crossover region, when VIN is slightly below VOUT. It could be possible that the device jumps back and forth between standby and operation mode due to the load transients, leading to risk of irregular switching behavior.
We would need to investigate if irregular switching behavior can lead to stronger oscillation on the leading/falling SW edges.

3. I cannot fully answer this question either. If the load is consistent without transients, I can only assume the crossover between operation and standby state when VIN > VOUT is also more "clean", meaning the device does not jump back and forth.

Best regards,
Niklas

Hello Niklas,

thank you for your answer.

Real life measurement

We repeated the SW pin measurement with a resistive load (Vin = 24 V). For this measurement, we used the best probe available to us and minimized the probe loop area as much as possible. We measured directly at the SW pin of the chip. Despite these precautions, I suspect the measured undershoot may appear somewhat larger than the actual value due to remaining probe-induced artifacts. If the undershoot were truly this severe, I would expect the IC to already sustain damage under these conditions.

Tina TI Simulations

We also performed simulations using TINA-TI. When adding realistic parasitic inductances to the model, we observed similar—or even worse—ringing behavior on the SW pin.

The simulation file is attached for your reference:

webench_design_TPS43061_SW_ringing.TSC

Open Questions

1. Simulation Results: Why does the simulation also show such severe ringing? Did we model something unrealistically, or did we select inappropriate component values? We tried to follow the recommendations from the datasheet and the Webench tool as closely as possible.

2. Expected Damage Threshold: If we are already measuring this level of ringing in real-life operation, shouldn't the IC be damaged at much earlier operating points rather than specifically at Vin ≥ Vout?

3. Alternative IC Recommendation: Are there alternative boost converter ICs that handle the Vin ≥ Vout crossover condition more gracefully—for example, devices with a dedicated bypass or pass-through mode? If so, which device would you recommend for our application?

Kind regards,
Jacob

Hello Jacob,

Thanks for all your investigations.
1. There are a lot of factors that influence the switch node ringing. MOSFET selection, layout, gate driver strength, gate resistance, snubber placement, etc.
Often the main root cause cannot be pinned down easily and optimization via trial & error with snubbers is necessary to achieve acceptable performance.
For a new revision, I would recommend to already place footprints for gate resistors and RC snubbers to give more options in ringing prevention.

2. The abs max limitations give the range where the device is verified and tested for proper operation. If the spikes go outside this range, damage is possible, but we cannot determine if and when damage happens. Even with undershoots of -5V, damaging the device is not guaranteed, but the risk increases with each spike, as the internal components are under extreme stress.

3. Our newest synchronous controller device would be LM5126A. This device uses our newest technology and comes with features supporting bypass operation and smooth transitioning.

Best regards,
Niklas