Part Number: TPS546E25
TPS546E25 FAQ
Q: I write to registers 0x33 and 0x46 to update the switching frequency and overcurrent limit in NVM. After issuing STORE_USER_ALL and RESTORE_USER_ALL, the register values do not change. Why?
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Part Number: TPS546E25
TPS546E25 FAQ
Q: I write to registers 0x33 and 0x46 to update the switching frequency and overcurrent limit in NVM. After issuing STORE_USER_ALL and RESTORE_USER_ALL, the register values do not change. Why?
Several register values depend on both, see table at bottom:
The PIN_DETECT_OVERRIDE (0xD8) setting and The external pin-strap resistor values (MSEL1, MSEL2, VSEL, PMB_ADDR)
For the TPS546E25, the default value of PIN_DETECT_OVERRIDE is configured to use the pin-strap settings.
When this default is active, the device use the resistor-strapped configuration over the NVM-stored values.
Important Device Behavior
Certain commands are dependent on pin-strap configuration. Refer to the datasheet table listing commands affected by pin strap resistor values.
The effective register value depends on:
Primary internal divider configuration
Primary external divider configuration
Secondary configuration
Pin-strap settings
NVM contents
Example
After power-up:
If register 0x33 is written to 0x3806 (800 kHz)
And PIN_DETECT_OVERRIDE (0xD8) remains at its default (pin-strap mode)
The readback value will reflect the pin-strap resistor setting 0x3805 (MSEL2 <1.78kOhm), not the NVM value.
However:
If 0xD8 is changed to enable NVM control (for example, 0xD8 is 0x8E59 where Frequency_Switch and IOUT_OC_FAULT_LIMIT are sourced from NVM)
And register 0x33 is read as 0x3806 (800 kHz)
Then the value reflects the NVM configuration.
Similarly, if the MSEL1 pin-strap resistor is < 1.78 kΩ, the OC limit is set to 50 A, which will match the programmed NVM value.
Summary
If register values appear unchanged after STORE/RESTORE commands:
In default operation, pin-strap settings override NVM values.
