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UC1843: Trouble understanding artificial ramp on Fig. 7-13 of the datasheet

Alejandro López.Mazarías
Prodigy 10 points

Part Number: UC1843

I am working on the design of a step-down DC-DC converter which feedback loop I want to implement externally. This loop works best with a modulator using an artificial ramp (i.e. not derived from an inductor current) with its slope proportional to the input voltage. I had drafted this:

image.png

However I then saw this on the datasheet:

image.png

I do not understand why all this circuitry (instead of a resistor divider) given that on the block diagram the pin ISENSE is depicted as an input (presumably high impedance). I have concerns that I am overlooking something and my draft will not work.

Additionally, I am unsure that the circuit on the datasheet works well in the low duty cycle region (which I need to use because I have low output voltage) because, to me, the 2N2222 B-E voltage drop would result in a low voltage at the ISENSE pin for a short while after the timing cap C_CT is reset. The way I see it, in order to have a correct slope right after resetting the capacitor, you would need to raise the capacitor minimum voltage:

image.png

Many thanks in advance for any comments.

  • 0
    TI__Genius 9925 points

    Hi Alejandro, 

    The circuit shown below,

    provides a constant current source for C_CT. This makes it so that the the RT/CT pin has an idealized sawtooth ramp, as opposed to a non-linear RC-dependent ramp. This provides better control of the duty cycle in voltage-mode control.

    The other circuit shown below,

    simply takes a stepped-down copy of the RT/CT voltage, without altering the impedance seen at the RT/CT pin.  If a simple voltage divider was used here, then the frequency set by the combination of the R and C would be altered. This circuit is needed to prevent altering the impedance at the RT/CT pin. 

    Let me know if this makes sense. 

    Thanks,

    John

  • 0 in reply to John Gomez
    Prodigy 10 points

    Hi, John, thank you for your response, it is insightful, useful and appreciated.

    I now understand the circuits well. However, I am still confused about what I described by the end of my previous post (last diagram, low duty cycles vs. slope seen by the ISENSE pin when the timing cap has low voltage). Your informed opinion would be very helpful because I am considering adding this 2N2222 but my circuit will need to operate in the low duty cycle region so the modulator ramp (as seen by the ISENSE pin) needs to be correct there.

    Thank you.

  • 0 in reply to Alejandro López.Mazarías
    TI__Genius 9925 points

    Hi Alejandro, 

    How low is your duty cycle expected to go in your application?

  • 0 in reply to John Gomez
    Prodigy 10 points

    Hi, John. It is a buck converter and I need D >= 5 V / 33.6 V = 0.148 as my input voltage range is 22 V to 33.6 V. Thanks.

  • +1 in reply to Alejandro López.Mazarías
    TI__Genius 9925 points

    Hi Alejandro, 

    Actually, for a no-load condition, your duty cycle will actually go even lower than 14.8%; close to 0%. The circuit configuration shown below should ensure that the COMP voltage can go below the ISNS ramp, which will ensure that the duty cycle can reach 0%.

    With this configuration, the minimum ISNS voltage is around 350mV and the maximum is around 1.65V. When the duty cycle needs to go to 0%, COMP will simply go below ISNS. When the duty cycle needs to go to 100%, COMP will exceed ISNS.

    The minimum and maximum values of the COMP pin are shown below. It is important that to note that the inverting input of the PWM comparator is not the same as the COMP value - it is instead (COMP-. 7V)/3. The .7 V drop comes from the two internal series diodes while the 3 in the denominator comes from the voltage R/(R +2R) divider. 

    Thus, the max value of the inverting input of the PWM comparator is (6V-0.7V)/3 = 1.76V, while the minimum value is (0.7V - 0/7V)/3 = 0V. Thus, if the inverting input (proportional to COMP) can exceed the ISNS ramp it can reach 100% duty cycle. If the inverting input can go below the ISNS ramp, it can reach 0% duty cycle.

    Let me know if this makes sense. 

    Thanks,

    John

  • 0 in reply to John Gomez
    Prodigy 10 points

    Hi, John.

    Thank you for the thorough response. It is well understood, very useful and much appreciated.

    What I was missing is that that RT/CT pin discharges the timing cap to 1.1 V not to zero. That way the 2N2222 can "copy" a correct ramp despite its B-E voltage drop.

    I have been looking for this minimum value on the datasheet but only the peak-to-peak of 1.7 V is given (useful as it relates to the overall modulator gain dD/dV_COMP, together with the 1/3 divider).

    The two diodes I added to the design on the datasheet, shown on my sketch, were an attempt to introduce this offset.

    I understand that the error voltage can travel across the whole modulator ramp range correctly (but thanks for stressing it), but I was concerned that the ramp reaching the modulator "PWM comparator" would have an incorrect slope in its lower region.

    Best.

  • 0 in reply to Alejandro López.Mazarías
    TI__Genius 9925 points

    Hi Alejandro,

    I had forgotten to attach the latest schematic + simulation result that reflects my discussion point on the internal COMP voltages. Please refer to below:

    Thanks,

    John

  • 0 in reply to John Gomez
    Prodigy 10 points

    Thanks, John. Like I said, it's the other pin of the modulator comparator I had my eyes on but your simulation shows good margin resulting in correct slope in the low duty cycle region Thumbsup