• State Resolved
  • Locked Locked
  • Replies 12 replies
  • Subscribers 62 subscribers
  • Views 200 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS7A8101: output delay

TPS7A8101: TPS7A8101: output delay not always present

Vincent Salmon
Prodigy 10 points

Part Number: TPS7A8101

Hello,

I observe the same behavior as TPS7A8101: output delay - Power management forum - Power management - TI E2E support forums with a CNR = 470 nF.

However, as 470 nF is much higher than 2.2 nF, i expect to see the delay on all regulators, but i surprised because, on the same board, with a duplicated schematic for the regulator, the delay is not present for some power supplies.

How could you explaine it?

Best regards,

Vincent

  • 0
    TI__Expert 6775 points

    Hello Vincent,

    Please consult the technical paper 'Demystifying LDO Turn-On (startup) Time' where the turn-on time is explained in detail: https://www.ti.com/lit/wp/slvafx0/slvafx0.pdf

    Best regards,

    Daniel Esparza

  • 0 in reply to Daniel Esparza
    Prodigy 10 points

    Hello,

    Thank you for this document.

    However, I'm not sure it explains why I sometimes have a delay of close to 0 ms and sometimes a delay of 30/40 ms.

    Best regards,

    Vincent

  • 0 in reply to Vincent Salmon
    TI__Expert 6775 points

    Hello Vincent,

    There are multiple factors that affect the turn-on time of linear regulators such as: enable voltage threshold, undervoltage lock-out, the value of the capacitor tied to the NR pin (if available), a feed-forward capacitor (on adjustable devices), the impedance of the input power supply, the value of the input capacitor(s), the value of the output capacitor(s), inrush current, etc.

    In the specific case of the TPS7A8101, there is a quick-start circuit to quickly charge CNR, if present. At start-up, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage. Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended CNR value of 0.47 μF along with the 33-kΩ resistance causes approximately 80-ms RC delay. Start-up time with the other CNR values can be calculated as: (1) Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a CNR value greater than 0.47 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 100 ms. That is, if CNR is not fully charged during this 100-ms period, CNR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge. A low leakage CNR should be used; most ceramic capacitors are suitable

    Can you share your schematic and (if possible) the layout around the regulator?

    Best regards,

    Daniel Esparza

  • 0 in reply to Daniel Esparza
    Prodigy 10 points

    Hello Daniel,

    The P2V3 comes from a power supply board with switching regulators and we use a 1 m cable assembly between the two boards for the tests.

    The output supply two components with an additionnal decoupling of 20 µF.

    There is a ground plane just below the TOP layer.

    Best regards,

    Vincent

  • 0 in reply to Vincent Salmon
    TI__Expert 6775 points

    Hello Vincent,

    I am consulting with the design team on the subject and will provide more details soon.

    Vincent Salmon said:
    There is a ground plane just below the TOP layer.

    Is this an inner layer in the PCB, in addition to a ground pour on the top layer?

    Best regards,

    Daniel Esparza

  • 0 in reply to Daniel Esparza
    Prodigy 10 points

    Hello Daniel,

    OK, thank you. Yes, it's an additional inner layer.

    Best regards

  • 0 in reply to Vincent Salmon
    TI__Expert 6775 points

    Hello Vicent,

    Thanks for your reply. Please allow an additional 1 to 2 business days while I continue investigating the turn on time of the TPS7A8101.

    Best regards,

    Daniel Esparza

  • 0 in reply to Daniel Esparza
    Prodigy 10 points

    Hello Daniel,

    OK, noted.

    Best regards,

    Vincent

  • +1 in reply to Vincent Salmon
    TI__Expert 6775 points

    Hello Vincent,

    Since the regulator has two operating modes for light and heavy loads, a comparator switches between the two modes when the NR capacitor is above 2.2 nF. There is a VOUT step due to the tolerance of the internal error amplifiers and part-to-part variation. The step in VOUT will have high unit-to-unit variation and depend heavily on COUT and IOUT during start-up. Also, board-to-board variations can occur even with identical 470 nF NR capacitors due to soft-start timing and NR capacitor interaction variations.

    Key Aspects Affecting Turn-On of the TPS7A8101

    Component Tolerances:

    • Capacitor tolerance variations (typically ±10% to ±20% for ceramic capacitors)
    • Resistor tolerance in the feedback divider network
    • Internal device parameter variations within specification

    Physical Layout Differences:

    • Trace length variations affecting parasitic inductance and capacitance
    • PCB manufacturing tolerances
    • Component placement variations

    Soft-Start Timing Interactions:

    • The interaction between the internal soft-start circuit and the external CNR capacitor can vary slightly between devices
    • Temperature differences across the board affecting component behavior

    Additional Considerations with Feedforward Capacitors

    Since your design includes a feedforward capacitor (Cbypass) in the feedback network, this adds another significant time constant to the startup. The time constant for the feedforward capacitor equals the parallel resistance of the feedback divider times the feedforward capacitance. A 470 nF feedforward capacitor can contribute approximately 4.5 ms to the total startup time.

    Recommendations to Achieve Consistent Behavior

    To reduce the delay and achieve consistent startup behavior across regulators:

    Option 1: Reduce CNR Capacitor Value

    • Change the CNR capacitor to 2.2 nF or less to eliminate the delay 
    • This will achieve startup times under 5 ms consistently

    Option 2: Adjust Design Parameters (if delay must be maintained)

    If you need to keep the larger CNR value for noise performance, you can adjust the delay characteristics:

    Parameter
    Effect on Delay
    CNR Value
    Larger CNR → Longer flat region duration
    COUT Value
    Larger COUT → Smaller amplitude (50-200 mV for 1-50 µF)
    Load Current
    Larger load → Smaller amplitude

    In summary, the inconsistent delay behavior you're observing is caused by cumulative variations in components, layout, and device parameters. While the schematic is identical, small variations in these factors can push some regulators above or below the threshold where the flat region becomes visible. For consistent, predictable behavior across all units, reducing the CNR capacitor to 2.2 nF or less is recommended.

    Best regards,

    Daniel

  • 0 in reply to Daniel Esparza
    Prodigy 10 points

    Hello Daniel,

    Thank you for your detailed response.

    Best regards,

    Vincent

  • 0 in reply to Vincent Salmon
    TI__Expert 6775 points

    Hello Vincent,

    You are welcome.

    Best regards,

    Daniel