Hello,
I want to monitor a clock presence and thought about using a supervisory IC with a watchdog input, like the LM3710.
I've some questions about this one:
- Is there a minimum WDI period/low time/high time requirement for the WDI transition detection?
- After watchdog has engaged reset, how can this signal be deasserted? From the figure 1, I think that it is after tRP laps following one of this event : VCC higher than VRST+VRSTH, MR higher than VMRT+VMRTH or WDI transitions? (Hence, using this IC with a uP, the only way to restart is to cycle power or push an MR button?)