TPS40192 operation at low VDD

Hi Aaron,

The UVLO off-threshold should be way below 4.88V, ~3.4V typical. So I don't think the shut-down is caused by the drop on Vin. Another possibility is the Short Current Protection (SCP) may get falsely tripped. You may check the SW waveform. If there is some switching activity followed by every 50-ms timeout, then that is probably due to the SCP. For debug purpose, you can try to remove R9 to double the SCP threshold. If the part can work with increased SCP threshold, I think there might be excessive noise on SW messing up the SCP circuit. BOOT resistor (R13) can be increased to 2~5 ohm to slew down the turn-on of the high-side FET in order to reduce the turn-on noise on SW.

Regards,

Na

Hi Na,

Thanks for the feedback. I first tried removing the SCP resistor. There was no noticeable change in behavior. I then tried inserting a 3.3ohm resistor in place of the zero ohm resistor at the BOOT pin. This time the behavior was much worse. Even at a nominal voltage of 5.0V the output never stabilized. It constantly started up then shut down.

Question about the SCP circuit... Information in the specification seemed to indicate that the SCP threshold value is only associated with the low-side FET. And the high-side FET short circuit threshold is fixed. Is this true? If so, maybe I'm seeing an issue with the high-side SCP, since none of the suggestions seem to have an impact.

I'm going to keep looking at this and would appreciate any feedback you have.

Thanks again,

Aaron

Hi Aaron,

Yes, you are right that the high-side FET short circuit threshold is fixed. So if increasing the low-side FET SCP threshold does not help, it could be due to the high-side SCP.

If increasing the BOOT resistor can make a difference, it also indicates that the shut-down may be caused by the high-side SCP. Because the BOOT resistor slows down the SW rising up speed and alters the profile of SW waveform, hence affects the high-side current sensing. I think increasing the BOOT resistor is the right direction to go to fixed the high-side SCP false triggering though.

Since the high-side SCP limit is 550mV, if that being tripped, I would assume you could see severe noise on SW when the high-side turnning on. My guess is the 6x47uF input cap is not closely placed between the drain of high-side FET and the source of low-side FET. This input loop carries switching current and needs to be physically as compact as possible.

Another thing to suppress the SW noise is to add series connected resistor and capacitor, i.e. a passive snubber circuit, between SW and GND close to the low-side FET. You may start with 1ohm+1nF.

Regards,

Na

Hi Na,

I tried two different resistor values in the BOOT path, 3.3 and 1.1 ohms. In both instances the performance of the circuit degraded. Basically the 0.9V output never turned on with a 5.0V VDD.

The high-side capacitors are located directly beneath the FET on the opposite side of the board. We have multiple HDI and CORE vias per capacitor. The VDD net is a plane. We have multiple GND planes in our stackup.

I tried a snubber circuit between SW and GND. I used a 1000pF capacitor with both 2.2ohm and 1.1ohm. There was no noticeable performance with either RC combination. The circuit was placed very close to the SW pin.

Below are a few scope traces. I believe the moment when the output voltage turns off is approximately the time when our digital logic tries to initialize. It would seem we are on the correct track but nothing I'm doing on this end seems to improve the behavior (other than increase the operating voltage, which is not an option in our final design).

Thanks,

Aaron

Hi Aaron,

Can you isolate the digital logic for debugging purpose?

Regards,

Na

Hi Na,

Yes, I can. I've isolated the load (the 5x100uF tantalum and 1x10uF ceramic capacitors are still present) and the output is stable down to an input voltage of about 4.6V. Below that, the output voltage does not remain at the 0.9V level. Once the input voltage reaches 4.6V, the output voltage decreases almost linearly as the input voltage is decreased. I would have expected the output voltage to remain steady down to an input voltage of about 4.5V, especially with no load.

Aaron

Hi Aaron,

The Vgs,th of the power MOSFETs is relatively high for 4.5V input. The Rds,on goes up dramatically, which could also cause problem for SCP.

Can you try other FETs with lower Vgs,th?

Regards,

Na

Hi Na,

Yes, I see your point. I am going to try to get samples of BSC080N03LS. The Rds-on is much better for a lower Vgs and Vgs,th is lower.

Thanks,

Aaron

Hi Na,

I was able to obtain samples of the BSC080N03LS part. With this part in place of the BSC110 the regulator performs much better. I can see the output is stable to well below 4.5V. Thanks for your help.

Regards,

Aaron

Hi Aaron,

Great! Glad it works now and thanks for the update!

Regards,

Na