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TPS63031 - PCB Layout Example

Other Parts Discussed in Thread: TPS63031, BQ24230, TPS63030EVM-417

Hi all,

I'm working on my first PCB design project, and I'm using the TPS63031 with the BQ24230 as a front end.

I was hoping you guys could show me an example PCB layout that separates the PGND and GND for the TPS63031.

Also, if you guys have any documentation showing how to successfully isolate grounds I would appreciate any sharing.



  • Here is the layout thus far, please critique.

    The rest of the mixed-signal circuitry is above what's picture.

    I am using 4 layers: SIG GND PWR GND

    How could I split that GND plane to ensure isolation from the rest of the circuit?

  • Welcome to the e2e forums.  There is a ground rules post at the top of this forum that you should read to get the best experience.  One item I would like to draw your attention to is the titles of your posts.  Please begin the title with the part number in question.  We have thousands of parts here, so this really helps let everyone know what your post is about.

    There is layout information in the datasheet.  You can also use the EVM as a reference layout.  You should tie all the TPS63031 related grounds from its components together at the thermal pad.  So, route those input/output caps directly to the thermal pad.  I would flip your VINA cap 180 degrees so its ground ties back to the GND pin.

    By the way, your inductor footprint is way too small.  You'll need a larger inductor.

    Make sure to check your trace widths and use large copper pours for the power traces (Vin, L1, etc.).

  • Hi Chris,

    Thanks for the response. I have read the ground rules and all future posts will abide, very sorry.

    Here is an updated layout, with a better suited "power inductor" (thanks for pointing that out!).

    There will be no more than a 200mA load.

    I have poured over evaluation modules and I have a hard time understanding how it works, and therefore how to apply it to my layout. Is there any TI documentation that might explain what is happening in those?

    With this layout, is there any need to split the internal GND plane? This circuitry is at the board edge and all of the devices are above it, both analog and digital.

    Also, are ceramic capacitors ok to use with this configuration?

    Thanks so much.

  • You just need to compare to or copy from the layout the IC that you are using.  That would be this one:

    You should make the ground pours from the input cap and output cap to the IC as wide as possible.  Compare to the EVM above.

    With this layout, there are few grounds and all are easily routed back to one point.  This is what's key.  So, there's no need to split grounds.

    The datasheet addresses your question on capacitor type.

  • Chris,

    What about in the case where I have a 4 layer stack, SIGNAL GND PWR SIGNAL?

    If the thermal pad is being tied directly to the GND plane, does that mean I now have to split the ground plane, so that I isolate that noisy thermal pad?

    It looks like they are doing something similiar in the EVM:

  • The key is that you just tie the ground of the IC and its components to the system ground plane at one spot.  So, in your design, this would be the thermal pad. 

    In the EVM, there were a few components that were referenced to the signal ground, so these were connected together first, then connected to the GND pin which was connected to the thermal pad.  The thermal pad was still the single point ground.

  • So I basically bring all IC related components to the thermal pad, which is directly tied to my continuous (non-split) ground layer?

    Do you think the 3.3V will need special attention, or simply dropping it down to the PWR layer for the rest of the board will suffice?

  • Yes, just keep the full internal GND plane.

    Once the output voltage is past the output caps of the TPS63031 it is just a DC signal with some current.  So, make sure your traces and vias are designed to carry this current and reduce the inductance and voltage drop in this path.