Working on an implementation of UCC35702D as a off-line buck convertor. Having issues with achieving 99% duty cycle.
1. Output level is controlled by introducing voltage to the VSclamp pin. I can control VSclamp from 0 to 3V.
2. FB pin is connected to Vref via a 1K resistor. FB sits at 4.90V.
3.VFF is, at present, set at 0.8Vdc. VFF is developed from a divider chain connected to the B+ rail which is running at ~169 Vdc.
4. Rt / Ct set to give an oscillator at ~90KHz.
As stated, VSclamp is adjustable from 0v to 3.0 Vdc. The duty cycle of the output on pin 4 readily changes from 0-80%. The output is not driving FET gates at this point in order to allow for an orderly startup and debug.
The data sheet for UCC35702D, on page 6, states that the maximum duty cycle is realized when the feedforward voltage is set at the low end of the operating range (VDD = 0.8V). The other 35702 pins are being held at the specified values.
Any help would be appreciated.
Thanks.