Using the circuit in Figure 10 on Page 9 of the UC3823A spec sheet does not work on the bench or in simulation at 19.5 kHz unless replacing 39pF with 4700pF, 120 ohms with zero and 22 ohms with 16 ohms. Using Rt = 42.2K, this also violates the required 10 to 15% range requirement on how far below the input frequency the slave unit should be "programmed". The idea of programming the frequency of the slave unit is ambiguous, since the free running frequency is altered by the presence of the resistor to ground in series with the timing capacitor on pins 6 and 7, so it isn't clear which frequency is being "programmed" - with or without that resistor to ground. If I simulate at 400 kHz as shown in the spec sheet with Rt = 3.65K and Ct = 1nF for the master, and Rt = 4.11K, Ct = 1nF for the slave, I find that it just barely works. Sync is lost if Ct decreases by more than 2%. On the other hand, sync is OK for Ct increasing up to 70%, so in this case it makes sense to center Ct at 1.34nF, giving a +/-27% range of acceptable values. Has anyone else wrestled with this issue and worked out the spec sheet discrepancies? What are upper and lower limits on allowable peak voltage levels at pins 6 and 7?