I already know that our VC1 and VC2 are connected to the wrong cells, so, please ignore that part of the design. It doesn’t have any effect on my question. Please see attached schematic.
What if the enter balance and exit balance thresholds are both at their negative most tolerance ( -9mV for exit and 15mV to enter)? If one cell becomes more than 15mV above the other, balancing will turn on until that cell is 9mV below the voltage of the lower cell. At that moment, what was the lower cell is now 9mV above what was the higher cell. There is only 6mV of margin for the original lower cell to now trigger balancing as the higher cell. Could noise or reading accuracy cause this condition to begin balancing? If so, wouldn’t the balancing alternate between the cells until they are both fully depleted? I am concerned that this condition may happen. Is there some aspect of the chip design/functionality not mentioned in the datasheet that prevents this scenario from occurring?
Thanks for your help!
4062.QB29200 Cell Balancing Question Schematic.docx
Regards,
John