UCC28061 / UCC28063 spontaneous gatedrive turn-on after turn-off

I've added some extra Y-caps and it's stable across 30-130KHz. Sadly, still violent spontaneous switching.

i've now minimized the layout and came to the conclusion that when the controller decides it wants to turn on phase B again (turning B off and running on phase A works fine), it also fires phase A simultaneously. I can recreate this behaviour when controlling PHB externally. on the trip-point voltage where B should join in, phase A fires again, resulting in very large currents. The controller doesn't return to stable dual phase operation at all.

Anyone?

Hello Floris,

Look for noise or interference coupling into one or both of the ZCD inputs.  A noise "glitch" on these inputs can prematurely turn ON a gate-drive that normally should be off. 

In an ideal environment, the ZCD inputs work like this:
When the on-time for GDA, for example, is completed and the Phase MOSFET is shut off, the current inthe inductor demagnetized and the ZCDA voltage swings positive during this demagnetization time.  When ZCDA rises above the 1.7-V threshold, it "arms" that phase to turn on again once the zero-current detection (ZCD) crossing happens.  This crossing is defined as when the ZCDA signal swings back negative and falls below the 1-V turn-on threshold. 

The ZCDx signals are usually derived from sense windings on their respective inductors (often relatively remotely located from the controller).  In the real world, the windings or the signal-track loop can pick up switching noise either from the other phase or from some other nearby power circuit.  If this noise is large enough, it can drive the ZCD signal below 1 V and turn that phase on before it should.  I think this is what appears to be happening in your system.  Phase-B's turn-on switching couples negative-going noise into ZCDA and triggers GDA to turn on again before its inductor has demagnetized.  This problem can exist for either Phase A or Phase B or both at the same time.  Careful signal routing is necessary to prevent this, including running the GND return for each ZCD winding back to the IC on a separate closely-spaced track parallel to the signal track.  Avoid connecting the ZCD-winding GND directly into a convenient nearby high current return path, which are often near the inductors and some distance from the quiet IC GND. 

The ZCD inputs use current-limiting resistors in series with the windings, and a small capacitance to adjust the ZCD timing.  Avoid increasing these cap values for better "noise filtering".  They are not filters, but are intended to precisely set the turn-on timing to implement BCM (or as TI calls it: Transition Mode - TM).      

I hope this helps you to debug your system.

Regards,
Ulrich 

Hi Ulrich,

Recently we've found cause and solution. To remind everyone reading: i'm using this PFC controller in a BCM Buck converter application.N-MOSFETS are high-side, source at output & inductor side.

There appeared to be one problem, but there were actually two.
- The first one is described above (even when PHB disabled, phase A goes in spontaneous CCM)
- The second one looked to be the same problem (phase A going in CCM) but wasnt.

The first problem got solved when lowering the dV/dT-limiting capacitance and replacing the driver with a combination of a much more robust IR2113 as levelshifer + TC4452 as current driver. The original IRS21850 was exceptionally sensitive for negative gatedrive signals, and was creating havoc at the controller, triggering resets etc.

The second problem exhibits the same behaviour, but did not occur with PHB disabled.This post is about how the second problem got solved too.

---It appears that when the controller tries to turn on phase B, it also switches phase A simultaneously on. This also happens with artificially induced (or none for maximum Tper) ZCD, VSENSE,  VINAC/CS at a fixed "OK" level and externally forcing PHB to trip between one and two-phase mode. I've made some 'scope printscreens and can post them monday if you want. Only after the first ZCD comes, phase-shifting starts. If no ZCD comes, simultaneous restarting continues. This behaviour is a fact.

This behaviour is strange on itself, but should not be as destructive as it is. However, i've made a mistake in my bootstrapcircuit where phase B cannot create a bootstrap-supply. Both MOSFET sources are connected with eachother through the inductors and because of that, when the output is at anything higher then 0volts, phase B can never restart. Thus, with the controller restarting over and over, phase A goes fully CCM with destructive results.

Previously, we've never checked if the MOSFET from phase B actually did turn on when going from single to dual phase, because clearly it worked when starting in dual phase mode (because both MOSFET sources were at 0 volts when starting!). The only thing we saw was phase A and B working perfectly as they should, then disabling phase B,  then trying to turn phase B back on and then phase A going full CCM and blowing its driver and/or controller.

When ensured phase B could actually turn its MOSFET on by using a charge pump, this phenomenon never returned. Phase transition  now works as nicely as it should. I know the true pupose of the ZCD resistor/capacitor network.

So both problems now seem to be an user fault and/or wrong choice of components. For now, only one question remains.
- why does the controller turn on both phase A and B at the same time when transitioning from one to two-phase operation?

Hi Floris,

That is an intriguing use of the PFC controller to operate in a buck topology.  Certainly some unexpected issues were bound to surface, and I'm glad you were able to find and debug them. 

The UCC28060/61/63 series of interleaved controllers use a phase-locked-loop to maintain the 180-degree phase shift between each output.  Since transition mode (boundary conduction mode)  results in widely varying switching frequencies, the PLL continually adjusts the on times for each phase to stay 180 degrees apart. 

However, the PLL needs to acquire the phase relationship before it can adjust it, so the initial start-up of the two phases start at the same time and the PLL is able to shift them to 180 after a few cycles.  This happens in 4 situations: at initial start-up, when Phase B is re-enabled using PHB input, recovery from an over-current event, and if the ZCD signal is lost.

All 4 cases are related to the ZCD signal.  The PLL uses internal gate-drive signals, not ZCD, to effect the phase shift.  But there will be no gate drive for an output if there is no preceeding ZCD input signal.  At start-up, there is an internally-generated start pulse for both phases reccurring at 200us intervals.  Once the phases start swtiching, they generate their own subsequent ZCD signal necessary to trigger the next switching cycle, consequently: TM (BCM) operation.

When PHB turns Phase B off, its ZCDB signal is lost, so when PHB is toggled high again, the internal logic starts it in-phase with Phase A and the PLL shifts them to 180 in a few cycles.   
 If an overcurrent condition is detected at the CS input, both phases are immediately shut off and stay off until the CS input voltage drops below 15mV to ensure that the inductors are substantially demagnetized.  The restart ends up in-phase again (see page 19 of the UCC28061 datasheet and page 30 of the -063 datasheet).

Finally, in the case of instantaneously low output voltage (due to excessive ripple or heavy load step), if the peak of the highest high-line approaches too close to Vout there may not be enough voltage difference developed on the ZCD windings to cross the input thresholds necessary to trigger the next gate-drive pulse.  Switching stops and does not resume until an internal automatic start pulse occurs after 200us.  If the ZCD voltage is still inadequate, you can see a series of restarts about 200us apart until the output-to-input voltage difference increases enough to restore the proper ZCD signal level and maintain next-pulse triggering.   The PLL can then restore the 180 phase shift as well.

So the in-phase start-up behavior is a fact, as you say, although temporary and brief.  I hope I've explained why and when this can occur.  I'm not sure if there are any other ramifications when operated in a buck topology.  I hope you've found all of the nuances involved with adapting the PFC controller to interleaved buck convertion and enjoy smooth progress to production.

Regards,
Ulrich 

Hi Ulrich,

Many thanks for your reply. It explains why the on-time changes with the input voltage.

One additional question: are the on-times during restarts different between phases A and B? In my case, the phase A on time is ~ 50us whereas that of phase B is only ~ 15us. Tset is 330k, which implies a Kt of ~ 10us/V. Vcomp is consistent at 2.4V and VINAC is stable at 3.5V (out of the additional on-time range?) VSENSE and HVSEN are tied together at ~ 1.8V (36uA source turned on) an PHB is tied to VREF at 6V (2 phase operation). Although, there's no MOSFET tied to the gate outputs, Vcs floor noise is below 20mV. Is there any additional handle that determines the restart on-time?

Thank you.

S.K.

Hi Ulrich,

Many thanks for your detailed explanation. I forgot to mention that both phases fire at the same time as pointed out by you.

I have trouble with erratic startups under full load with this asymmetry because the overcurrent sensing will cut off the high Kt phase prematurely while the low Kt phase is too short. As a result, there's not enough voltage to kick in the zero crossing (1.68V) and change the PLL error signal.

Maybe one way out is to reduce the TSET resistance, but I wish to keep it at 330k in order to cap the maximum switching frequency to ~ 180kHz. Is there anything I can do to the TSET input in order to reduce this asymmetry, at least during start up? I'm guessing that putting a series RC in parallel to the RTST resistance harm the operation could work, but to be sure, it would be nice if you could shed some light on the internal mechanics of this specific pin.

Thank you again.

S.K.