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TPS5450 instability & outright failure @ certain Vin voltages

Other Parts Discussed in Thread: TPS5450, SWITCHERPRO

I have the following TPS5450 circuit designed into a new product:

Design is for Vout of 5.6V at up to 5A over a Vin range of 8V to 30V, and SwitcherPro says it'll work fine.  I've checked the datasheet equations too and have found nothing that would indicate that I might have a problem.  But we just built up the first prototypes last week and I'm seeing some *very* strange behavior.  The regulator works fine when Vin is between 8V & 10V, and when Vin is between 15V & 20V.  But outside of those ranges I see two very distinct failures....

1. If Vin ever exceeds ~20V or so, the TPS5450 fails permanently with a hard short between its Vin and GND pins (measures just over 1ohm between Vin & GND after failure).  This is irreversible, and only by replacing the TPS5450 chip can we get the regulator circuit to work again.

2. Whenever Vin is between 10V & 15V, the output jumps to 6.3V, and the waveform at the PH pin is like nothing I've seen.  Here are scope shots of the regulator waveforms in the three different Vin operating ranges:

In all three scopeshots:  The bottom (yellow) trace is the PH pin.  The middle (purple) trace is Vout.  The top (green) trace is Vin.

The top & bottom scopeshots shows "as expected" behavior with Vin at around 10V & 17V respectively.  The middle scopeshot shows erroneous behavior with Vin at around 12V.  I'm dumbfounded by this behavior.  The TPS5450 regulator should have a fixed frequency variable duty-cycle behavior across its entire operating range.  Why is it behaving so strangely at voltages between 10V & 15V here????  Note that these plots are taken with an 8ohm load connected between Vout and GND, but I've tried other loads and I always see this odd behavior whenever Vin is between 10V & 15V.

So....  WTF is going on here??  I've always had good experiences with other TI switchers I've used, and I've never seen anything at all like this behavior.  We seem to have two completely independent failure modes here, and need a solution to both.  We're already behind schedule for this product development, and need a solution FAST.  Would very much appreciate any assistance.



  • I'm not sure about issue #1.  The TPS5450 is rated for input voltage up to 36 V, so 20 V is well below the abs max.  Are you hot plugging the input voltage?  Or raising it slowly with an external supply?

    Issue #2 looks like it could be instability.  What is the ESR of the output capacitor?  The TPS5450 is internally compensated and the output filter doubel pole and ESR zero should align with teh internal compensation zeros and poles.  I have seen cases where other external components connected to the output voltage bus have caused unexpected behaviour.  I would measure the loop response just at the border of your stable region to see what teh crossover frequency and phase margin are.

  • Thanks for the quick reply John.  To answer your questions:

    No, I'm not hot-plugging these; I'm using a bench supply and ramping the voltage slowly up and down.  The moment I first hit ~20V the current draw went to the limit of the bench supply, so I quickly removed power.  So no, this is not due to overshoot on the Vin line exceeding max ratings caused by hot-plugging an inductive feed.  And the TPS5450 is actually rated for a 40V absolute max (not 36V) on Vin, so I haven't brought it anywhere even remotely close to its limit when it fails.

    For output capacitors I'm using seven (7) paralleled 47uF ceramic (X7R) capacitors with extremely low ESR.  The ESR of the parallel combination is incredibly low.  We're talking <0.01ohm per capacitor, for a parallel combination of <2 milli-ohm.  And the PCB design was done using planes to ensure very low impedance connections to these capacitors.  So no, I don't believe excessive ESR is the cause of the problems.

    You suggest that I "measure the loop response just at the border of [the] stable region to see what the crossover frequency and phase margin are".  I'm not sure how to do this.  I know how to get crossover frequency and phase margin in simulation, but have never had to debug the stability of a switcher design in hardware; I've always just designed to the datasheet requirements and verified in simulation, and until now that was enough to ensure that the design would work.  Not sure what I missed in this case.  Can you please describe to me how to measure the loop response in hardware??

  • If you are using ceramic output capacitors, then it is most likely a stability issue.   That part usually takes a POScap type with 25 - 40 mohms ESR.  There are a couple methods to measure the loop.  The easiest is with a dedicated network analyzer, but I suppose you do not have access to one.  If you do let me know which one, and I'll try to walk you thru the set up.

    For now I would suggest opening up your switcherpro design file.  You can replace that 330 uF output cap with what you are using.  The "what if" tab will allow you to get insight into the loop characteristics and you can see the modeled response.  If you post your actual schematic I may try it for you later tonight.  I no longer directly support that device, but I am very familiar with it.

  • Hi Grayson,

    One more thing to look at, in addition to the stability. What is the connection to the power supply like? If long leads are used a bulk cap may help on the input to the board. On the second screenshot there is a lot of movement VIN when in the unstable region. Are there oscillations on VIN with the higher input voltage due to the lead inductance? From the description of the failed part, with VIN shorted to GND, it makes me think over-voltage occurred on the VIN pin.

    However it appears stability is the main issue due to the very low ESR output capacitors.

    Best Regards,

  • I did some checking with switcherpro.  With those ceramic output caps, your phase margin should be around 35 degrees.  While I probably would not recommend that for a final design, it should be good enough for your supply to operate.  If I know your upper resistor divider value I can suggest a feed forward capacitor you can try.  It may possibly be the input capacitor or some layout issue though.  Can you post your actual schematic and layout? 

  • OK, my complete power supply schematic is below.  Layout is not as easy to post, but I can assure you that it's clean; loops are small, impedances are low, etc.

    Note that all caps not labeled "NP0" are ceramic X7R dielectric.

    I'm beginning to suspect that the input filter may be to blame for some of the problems.  I just got some replacement TPS5450 chips in this morning, and one of the first things I'm going to look at is to see how things behave when I apply power directly to VinFP/GND rather than to Vin/Vreturn, thus avoiding the input inductors & common-mode choke.  Will post results.

  • No dice.  Behavior is the same when I connect the bench supply directly to VinFP/GND as it was when I had it connected to Vin/Vreturn.  So it seems the input filter isn't the culprit here at all.  Any other ideas??  You mentioned a feed-forward cap as something we might try?  I'm open to any suggestions.

    Also, we've been focusing on issue #2 from my original post, which you seem to think is due to instability, and I'm inclined to agree.  But I'm also concerned about issue #1 where the TPS5450 fails dead short whenever Vin exceeds ~20V or so.  I haven't tested this again after replacing the chip on my test board, but we've now seen 3 units fail in this way, and it does seem that whenever we apply >20V we see this failure.  Any idea what could be causing this??

  • The following app note gives guidelines to adding external compensation when using only ceramic output capacitors:

    Can it also be tested with VIN > 20V with the input filter bypassed to see if the part survives? (I am guessing only issue #2 was verified so far without the input filter)

    Another test would be to see the behavior when the part fails with VIN > 20V. Can you try increasing the VIN slowly and monitor VIN (at the IC), SW, and VOUT to see how the behavior changes before it fails? I recommend triggering on VIN to see if there are any unexpected spikes which exceed the 36V max. It would be good to also do this while increasing VIN > 20V with the input filtering bypassed.

    It might be possible to current limit the input power supply during these tests to avoid damaging the part so it doesn't need to be replaced.

    Best Regards,

  • I see you have ENA tied directly to VIN...abs max for EN is 7V.  I bet that is what is destrying your device.  It may also affect normal operation.  It has been a while since I worked with TPS5450, but I think the TPS5450 will act up if the EN pin is much above 7 V before it may be damaged.  ENA has an internal pull up.  To check this out just let ENA float.  If you need to modify the compensation I recommend that you ignore the app note referenced above.  Just try 2700 pF in parallel with the 10k upper resistor in the divider network.  Let me know if just the ENA alone fixes your issue or if you need the 2700 pF cap as well (I would be inclined to use the cap myself).

  • Good catch John. I had overlooked the VIN to ENA connection. It is known that if ENA is pulled above 7V (minimum, typical value can be higher) the device stops regulating properly. If driven even higher it can cause a failure.

    Also to elaborate on the app note, the equations work but it may add more components than is necessary for a stable system. For many cases, only adding a parallel capacitor is sufficient.

  • Great catch John!!  I completely missed that.  Wow.  OK, I've lifted that pin, and everything behaves correctly.  I can now ramp input voltage from 9V up to 30V and it regulates correctly with no strange behavior.  Thank you!!!!  :)

    To be thorough, though, I wouldn't mind cleaning up the feedback network to improve phase margin.  I've run through the app note and calculated the following values for the Figure 7 feedback network to match the inductor and output capacitor values of my circuit:

    R4 = 10K
    R7 = 2.8K
    C11 = 2700pF
    C12 = 0.068uF
    C13 = 150pF
    R7 = 1.33K

    But this 6-component feedback network does seem pretty heavy-handed.  Anthony suggests that I can get away with less, and I'm inclined to agree.  I'd be very happy to hear your suggestions for a smaller component-count feedback network that would still help ensure good stability over changes in system parameters (component tolerance, temperature, time, etc).  What would you recommend for a minimal feedback network to ensure good stability?

  • Glad to see this fixed the issue! Like John suggested, only using C11=2700pF may be sufficient. R7, C12 and C13 do not add much to the loop but in some cases are needed.

  • Thanks guys!  I think that about clears it up.  I've added tags and edited the subject of the original post to be more specific so others with similar issues might more easily find it.  I'll mark this as "answered" because I'm pretty sure we're good.  If I run into other issues I'll post back.

    Kudos for the great support!  :)

  • From my previous post a few up the thread:

    If you need to modify the compensation I recommend that you ignore the app note referenced above.  Just try 2700 pF in parallel with the 10k upper resistor in the divider network.  Let me know if just the ENA alone fixes your issue or if you need the 2700 pF cap as well (I would be inclined to use the cap myself).

  • Sorry for not being explicit earlier, but yes, just disconnecting the enable line did fix both of the initial problems without changing my feedback network.  But I still wanted to perform some further testing to check stability with and without the 2700pF cap in the feedback network.  Best way I could think of to test stability was with load transients.  So I set up a test to apply a 3 ohm load for brief durations.  What I found is that the stability seems to depend a lot more on input voltage and output loading than it does on that cap in the feedback network.  Below is what I saw.  In each case, the left plot is with no cap in the feedback network, and the right plot is with a 2700pF cap in parallel with the top resistor in the feedback network.  The noted load in each case (light load, 100ohm, 8ohm) is a steady-state load directly connected to Vout, while the 3ohm transient loading is only applied while channel 2 (green) in the plot is low.  Channel 1 (yellow) is Vout AC-coupled.

    Vin=10V, light load:

    Vin=15V, light load:

    Vin=20V, light load:

    Vin=25V, light load:

    Vin=10V, 100ohm load:

    Vin=15V, 100ohm load:

    Vin=20V, 100ohm load:

    Vin=25V, 100ohm load:

    Vin=10V, 8ohm load:

    Vin=15V, 8ohm load:

    Vin=20V, 8ohm load:

    Vin=25V, 8ohm load:

    So the cap in the feedback path doesn't seem to make much difference in stability, but the regulator really seems to prefer being more heavily loaded.  This is a little frustrating for me because I need to support a pretty wide range of load conditions.  I may have to add a fixed resistor to tame the regulator, which is unfortunate because it's going to burn unnecessary power.  If anybody has suggestions for ways around this I'd appreciate hearing them.

    Note that at Vin=10V load=8ohm, the response was very sensitive to small changes in input voltage.  So I think the differnces in the two plots (with and without the 2700pF cap) are more likely due to the input voltage not being quite the same, and should not necessarily be attributed to the difference in the feedback network.  Moreover, I'm inclined to ignore these two plots since this seems to be at the limit of the regulator's ability to operate.

    So should I include the cap in the feedback path?  It doesn't seem to do any harm, but doesn't seem to do much good either.  Open to suggestions.

  • What's the slew rate on the current step rising and falling edges?

  • Slew rate on the current step is fast.  I'm not really sure how to measure it with any reasonable accuracy.  It's a PMOS gated by a pulse train connecting Vout to a 3ohm resistor to ground whenever the gate is low.  Channel 2 in the scope shots is the gate of the PMOS.

    FYI I'm not that concerned about brief excursions of ±200mV or so from the nominal 5.6V in response to major load transients, as seen in many of these scope shots.  But I'm concerned if the behavior I'm seeing indicates borderline stability.  And maybe even more importantly, we absolutely cannot tolerate even very brief dips to 4.6V (1V below nominal) at any time because that would trigger a POR chip to reset our system.  And the load transients I'm applying are very much like what will be seen in normal operation of our system.

    Is this cause for concern?  Do I need to somehow slow down the load transients??

  • Really fast transients will require more output capacitance to support small voltage deviation.  As a general rule of thumb, 1 A/usec is considered a "fast" transient.  For my reference designs I usually use 500 mA / usec as the criteria for my test reports.