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TPS63002: High supply current for low load

Other Parts Discussed in Thread: TPS63002

Hi,

I am testing a board using a TPS63002 to generate 5V with a very low load (8mA) and the converter is pulling 42mA at a 4.8V input however based on the datasheet efficiency graph I should be seeing far greater efficiency of about 70%.

I have attached the relevant schematic and layout sections. When I first received the board there were significant stability problems, and the converter would frequently draw several hundred mA and fail to start properly, this instability seems to have been fixed by removing C20 and remounting it immediately to the left of the IC, connected to the power pad on one end and the output trace (with the mask scraped off) on the other. I have also added a 100uF electrolytic smoothing capacitor elsewhere on the board. However both of these had little to no effect on the supply current issue and has not worked on a second board I have modified, so any suggestions are much appreciated.

Is there any guidance for how to select components to reduce the supply current or are there values I should change? The application sees a roughly 5mA load with occasional spikes to 150mA max for several seconds. Is the layout likely to be the cause and is there any modification I can do to the prototype to confirm this?

Thanks.

7450.BadConverterSchematic.pdf  4338.BadConverterLayout.pdf

  • Yes, the input cap needs to be placed right next to the IC for best functionality.  You can order and look at the EVM for a good design and layout.

    You will need more output capacitance to ensure stability, per equation 7 in the D/S.  Keep in mind the dc bias effect which reduces the amount of capacitance that you actually have.

    In the layout, the FB pin is shorted to VINA.  Fix this, replace the IC, and retest.

    Finally, your power traces (VIN, L1, L2, Vout, PGND) are very narrow.  These carry the high switching currents and should be as wide as possible.

  • I have boosted the output capacitance to 20uF (by fitting another 10uF on the empty pad of C20) which doesn't appear to help with the problem. I am working on getting hold of larger capacitors to boost this further and the same with the input. I've got the EVM on order, I'll compare readings from that to my own board when it arrives.

    I don't understand what you mean about the FB pin shorted to VINA; by my reckoning FB is pin 10 which is shorted to pin 1 (VOUT). In the image I uploaded pin 1 is top-left and the image is mirrored (its the bottom-side of the board); is this correct?

    I will change the layout anyway to match the EVM, but are the narrow power traces likely to be the cause of my problems with high supply current?

    Thanks.

  • Ah, it's on the bottom of the board.  It was difficult to tell with the symmetrical layout.

    Your narrow traces and far C20 placement create extra inductance that might have damaged the IC from spikes during switching.  I would replace the IC, move C20 closer, and rerun your test with no load connected.  It's also important to evaluate just this one piece of your system by itself so that other pieces don't mislead your results.

  • I've run the tests with the EVM and seen the same supply current problem; it seems the 20uA reverse leakage across a power rail isolation diode was enough to switch on another part of the board, but not when the converter was bypassed. Adding a pull-down for the switch terminal was enough to solve this.

    Moving C20 closer and increasing the value, on a board which has never been powered up, shows the converter as more stable and the input current values make more sense, I will change the layout to match the EVM which should improve the stability. I'll mark your answer as accepted since it covers the part of the problem related to the DC-DC.

    Thanks.