NexFET poower MOSFET SPICE models from TI don't work for synchronous rectification

Kristian, 

I spoke with the author of our spice models and got the following response:

"High dv/dt at drain node causing Cdv/dt current through gate. Due to relatively large RG the device tends to turn on. Please try with longer rise and fall time. Adding RC at gate will also slow down the FET." 

Hope this helps. 

Hi Brett,

Thank you for speaking to the author of your SPICE models. However, I am afraid the issue has not been resolved:

The MOSFET turning itself on from Cdv/dt current through the gate should not cause the simulation to fail to converge. This is in fact one of the situations that I would like to be able to simulate.

To ensure that I am fully communicating my problem here so that we don't talk past eachother: I am talking specifically about the case of commutating current from the MOSFET channel to the body diode (please refer the author of your SPICE model to my step-by-step guide to reproduce the problem, as well as the attached Orcad Capture project.)

When commutating from channel to diode, the quick rise of the diode forward voltage drop should cause the MOSFET to turn on briefly - however, this is actually benificial as it will simply result in a momentarily slightly lower diode conduction loss. (in other words, it will just slightly reduce the dead time)

In order to get the previously attached simulation to converge, I need to slow the gate signal to down to a snail pace of 110ns fall time. Of course, your NexFET devices are specifically designed for very fast switching at high frequency, so such a slow gate drive would be completely unacceptable! And to reiterate, there is no reason why this sort of self turn on should cause the simulation to fail to converge, as I have simulated the exact same situation with many other fast MOSFETs...

Best regards,

Kristian

Kristian, 

I'm going to point you to our SPICE model authors. His name is Touhidur Rahmam.

trahman@ti.com

I have already forwarded him your message so hopefully he will have already thought about it when you contact him. 

hi  Kristian,

thank you for your interest on NexFET.

i ran your sample schematic in spectre. It completed simulation without any convergence issue. All simulators have some limitations. it is due to difference in algorithms and model eauations.

i understand your are having convergence issue in PSpice. You can try running in spectre. if you need any assistance on that I will be glad to help.

best regards

Touhidur

Hi Touhidur,

Thanks for taking a look at my model. Sadly, we do not have a Virtuoso/Spectre license available, and I doubt that it would make sense for us to acquire one for just this single case. 

However, since the SPICE models for the NexFET devices are clearly marked as PSpice models, both on the download site and in the model file, I am thinking that there must be some version of PSpice where you have actually gotten the model to run. It would be very nice if you could point me to this version of PSpice. 

If it really only works in Spectre, then I think it would make more sense to call it a Spectre model on the download site and in the model file rather than a PSpice model, so that your customers can 1) avoid wasting time and 2) actually manage to evaluate your product in their design by using the right tool. 

Thank you,

Kristian

Hi Touhidur,

Thank you for your expedient reply!

Increasing RELTOL seemed to fix the issue, also in capture version 16.3.

Once again thanks for your help and I look forward to playing more with your model :)

Best regards,

Kristian