Hello,
In my application, the SDI line is driven high (to 5V) using a strong pull-up. Consequently, I allow the SDI line to idle in the high state (to reduce power consumption) while not actively writing to the TLC59731. My implementation is as follows:
1. After writing all data, I wait for the GSLAT hold time.
2. SDI is then idled high for an indefinite time (at least 100us).
3. SDI is driven low and a new write sequence begins immediately.
My assumption is that the rising edge in step 2 will trigger the start of a new tcycle measurement, which will fail due to the period being too long. When step 3 finally occurs, the data is correctly being interpreted, so the rising edge from step 2 must have been correctly ignored.
My question is that I wish to confirm that step 3 will result in a new tcycle measurement. In other words, tcycle measurements will keep being attempted until a valid period is established. It would not be good enough for tcycle measurement only to occur at power up.
The datasheet doesn't really meantion abnormal cases like this.
Cheers, Ross.
