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# TPS40192： Undershooting generating to Vo.

Other Parts Discussed in Thread: TPS40192

By a circuit using TPS40192, undershoot occurs to an output voltage wave pattern the output side
in Vdd side power supply Off in no load, and negative electric potential may occur at one time.
It drives Low side Gate to ON then.
I want you to teach a probable cause, because I investigate the logic of the outbreak.

Condition:
a. The normal is Vdd=12V,Vo=1V
b. The output side to be in an electric discharge state, and to overcome that the input voltage is slow
in stop voltage neighborhood (Vdd=about 3.5V) of the IC is no load.
c. The drop time of Vdd more than 200mS/V.

Other information:
a. It does not occur by all means.
b. The switching wave pattern of the Gate drive stops once on the way and drives Low side Gate
c. In this time, I do not seem to influence it at descent time of Vdd.
d. The step of the middle electric potential of the COMP wave pattern lasts time of about 900μS.
e. The middle electric potential of the COMP wave pattern is about 240mV.
f. When Low side Gate becomes ON, COMP signal stands up by a chopping wave from 0V and falls into Low
when it became around 400mV.
g. The chopping wave start of the COMP signal is time of about 330μS to the voltage of around 400mV.
h. It is time of the about 1.2mS until it drives Low side Gate to the chopping wave start of
the COMP signal from the beginning.
i. Even if there is the resistance equal to 100kΩ between SW-BOOT listed with EVM board,
it occurs even if there is not it.
j. The oscillatory frequency of TPS40192 is approximately 610kHz.

Thanks,
Masami

• Hi Masami,

I think our FAE will contact you offline. If you have further question, please let me know.

Regards,

Na

• Hi Na

Thank you.
Although there is no additional information, I still need your help well.

Regards,

Masami M.

• Hi Na

I convey a result of the wave pattern observation by TPS40192EVM525.
As a result, I was able to acquire similar waveform.

Condition:
a. There is no fixed number change in TPS40192EVM525.
b. I connect electrolysis capacitor 470μF and two MLCC 22μF to the Vin side.
c. I do not connect load to the Vout side.
d. It supplies 12V to the Vin side.

CH1: Vin(TP1)   CH2: Vout(TP15)   CH3: LDRV(TP10)   CH4: COMP(TP6)

The mean voltage of Vout is around 0.2V outbreak at the time of phenomenon outbreak.
The undershoot is around 0.9V outbreak.
In addition, the COMP signals identify a similar wave pattern, too.

Please tell me the logic of the outbreak.

Thanks,
Masami

• Hi Masami,

After some bench test, we think the shut-down is caused by the voltage on BP5 lower than its threshold. After the TPS40192 shuts down, BP5 voltage will bounce back above the threshld again because the IR drop from Vdd to BP5 disappears, and then the TPS40192 restarts. If this voltage bounce-back is smaller, there is no shut down restart observed.

The ~1ms time when the COMP is held at ~400mV is the calibration time after the part restarts. It is followed by a pre-biased soft-start.

As one of the solutions, we tried adding 1kohm between BP5 and GND, when the device restarts, there is no PWM switching, hence no Vout dip.

Regards,

Na

• Hi Na,

Thank you, answer to outbreak logic.
I performed the same experiment and obtained a similar result.
By the way, there is an additional question from a customer.
Temporary shut down occurs and suffers from about 8mS until I drive Gate of the low side from a point considered that the voltage was restored of BP5, but please tell me the reason.
In addition, there is it, or how much may you estimate the time unevenness before driving low side Gate after the voltage of this BP5 was restored?

Thanks,
Masami

• Hi Masami,

I am not sure I understand the scenario of the shut down. Is the shut-down caused by extra loading on BP5?

Could you please provide some screenshots of the waveforms, like BP5, LDRV, COMP, VOUT etc?

Regards,

Na

• Hi Na,

I put a wave pattern of BP5 when there is no pull-down resistance on BP5 of the EVM board.

Ch.1 BP5, Ch2 Vout, Ch3 LDRV, Ch4 COMP

a-1. At the time of normal movement

a-2. At the time of phenomenon outbreak

I put the wave pattern of the following cases on the reference about BP5 of the EVM board.

Ch.1 Vin, Ch2 Vout, Ch3 LDRV, Ch4 COMP

b-1. no pull-down resistance

b-2. pull-down resistance 2.4kΩ

b-3. pull-down resistance 1kΩ

In addition, I put a wave pattern when there is no pull-down resistance on BP5 of the EVM board.

Ch.1 Vin, Ch2 Vout, Ch3 LDRV, Ch4 COMP

c-1. Vin outside capacitor 470uF + 22uF *2

c-2. Vin outside capacitor 470uF *2 + 22uF *2

Thanks,

Masami

• Hi Masami,

I think your question is focused on why there is ~8ms waiting time, right?

You can refer to the TPS40192 datasheet Figure 13 attached below:

After the switching shuts-down, the BP5 bounced back above its threshold immediately, so the TPS40192 is enabled right away. Then it gets into the 1ms SC threshold configuration time and COMP voltage is held at ~400mV. Then there is ~1ms time for the compensation network to get zeroed. After that, the part is allowed to start up. But because the Vout is still high, close to the regulation point, the switching will not start until the internal SS voltage is higher than the FB voltage. The soft-start time is typically 4ms, but the maximum can be 6ms. So the total time from the TPS40192 is enabled to Vout getting into regulation is 1+1+4 = 6ms typical, and could be ~8ms.

Regards,

Na

• Hi Na,

Thank you, answer to outbreak logic.
I performed the same experiment and obtained a similar result.
There is an additional question from a customer.
Please tell me minimum times before driving Gate of the low side after the voltage of BP5 was restored.

Thanks,
Masami