TPS54040A vs. LM25574 for inverting buck-boost

Hi Marc,

Both of these regulators are great parts and have a very similar feature set.  It might just come down to your preference for packaging and total BOM cost.  Both of them are Webench enabled to give you an idea of total solution size and cost.  Most likely they're not enabled for your inverting buck-boost topology, but you can get a good idea of performance and cost by running similar efficiency and transient Webench simulations.

Best Regards,

-Juan 

I have a few concerns about these regulators:

1) My load current may be as low as 10 mA.  Will this cause any problem?  Does that point to one of the two as better, or to yet a different IC?

2) I'd prefer not to have cycle skipping occur, due to possible noise effects.  Is there any way to avoid that at low currents?

3) The external clock circuit shown in figure 42 of the TPS54040A datasheet has the clock driving a 50 ohm load (to at least 2.2V).  This would require that the clock signal source at least 44 mA!!!  Is this really what is required?!

4) The LM25574 switches its Vcc LDO in and out at around 9V.  Although there is hysterisis, it seems like a bad idea to combine this behavior with a Vin of about 9V.  Should I just short Vin to Vcc for my application (my Vin will not exceed the 14V limit)?

5) The LM25574 datasheet cites a minimum load value of 100 mA to stay in CCM.  And the various graphs all show a minimum load of 100 mA.  Since my load will be as low as 10 mA, what will happen?  What are the implications of DCM?

Thanks!

Marc

I'm still very interested in getting the answers to the above questions....

Hi Marc,

Let me answer questions #4 to #5 and move the post to the Non-Isolated DC-DC so that the TPS4K team can help with answers #1 to #3:

4) If your Vin is just around 9V and won't exceed the 14V max, then yes, just tie the VCC pin to VIN.

5) When you operate at lighter loads then you will have the Discontinuous Conduction Mode (DCM) due to the inductor current hitting the zero Amp threshold.  This inductor will not be allowed to go negative by the external Schottky Diode, so it'll become discontinuous in nature.  In this state you'll have a Ton, Toff and Tidle, so the measured switching frequency will be lower than when it operates in CCM.

Best Regards,

-Juan

There is no way to disable pulse skipping on the TPS54040A.  The 50 ohm in the datasheet is what was used to test on the bench.  we were driving it with a 50 ohm output signal generator.  You can change that resistor to match your source.  Also you will need to level shift your SYNC clock.  The RT pin is referenced to -Vout for inverting buck boost applications.

In my application I'm concerned about noise.  I'm planning on syncing the power supply to one of my clocks.  If there is pulse skipping that may move the noise down into my frequency band of interest, so I'd like a design that doesn't pulse skip even at low loads.  I don't care too much about efficiency, but I don't want to have a big dummy load.  Can you suggest a synchronous converter that would stay in CCM with no pulse skipping?  My requirements are not that complicated: input 8-10V, output -9V at 10mA to 100mA, need to sync to external clock and maintain low noise.  What TI chip would you suggest?

In case I do use the TPS54040A, can you please explain the example external sync input circuitry?  The diagram in the datasheet doesn't entirely makes sense to me.  Why would you have both the 50 ohm resistor and the series RC circuit?  It would seem like either one or the other would be sufficient.  Since I need level translation on the sync signal, can't I just capacitively couple it, with maybe a larger capacitor and a zener diode clamp to protect the input from overvoltage?  If not, can you suggest a circuit that I can use to sync from a logic source in the inverting configuration, when my sync source will not be available until some time after power up?

Thanks!

Marc

Review the "Level-Shifting Control for an Inverting Buck-Boost" for the level shift circuits.

http://www.ti.com/lit/an/slva540/slva540.pdf

Yes, I've read that document.  But in my application the sync signal is not clocking at power up, and it is not in a known high or low state.  I need the power supply to start up self clocking, and then transition to synchronized clocking (this feature is available on other vendor's power supply chips).

It seems like I should be able to couple the sync signal to the RT pin through a capacitor, say 100 pF, and a series current limiting resistor, maybe 10k?, and clamp the voltage at the RT pin with say a 3.0V Zener diode.  And perhaps also provide a Schottky diode clamp to ground?

Does that seem like it would work well?  Please note that the application document that you suggested specifically says that it does not apply if the input clock signal might be held high.

Ac coupling is a good technique to implement synchronization.   The 100pF seems large, consider 10p to 22pf initially.  

Attached is a level shift circuit that will work with a clock power up state of high or low.   The resistors from RT to ground

sets the switching frequency before the clock signal is present.

7206.levelshifttps54060.pdf

I don't understand how the circuit you have provided works with both power up states.  If VSYNC is low, both transistors are off, and then the collector of the second transistor will rise to the voltage divider point of that string of resistors.  If that voltage is above the threshold, then it will inhibit self clocking.  And if it is below the threshold, then what is the point?

My mistake.   We have an archive a few level shift circuits and I pick the wrong one.  Attached is one that works and it is very similar to your earlier post.

5545.levelshift2_tps54060.pdf

Thank you, that is more or less what I had in mind.  What values would you suggest for the capacitor and the series resistor?

The datasheet does not provide many specifications for the RT/CLK pin that would allow the proper values to be determined.  What is the input impedance in RT mode? What is the input impedance in CLK mode? What is the current limit on the pin if it exceeds its voltage limits?

470pF 1kOhm have been used before with a ~247kOhm frequency set resistor.

The impedance in RT mode is low impedance, functions similar to a power supply 0.5V and ~10uA.

In CLK mode the impedance is high, input of a logic gate after the RT circuit turns off. 

The abs max table reads 100uA for the current limit on RT/CLK pin. 

With capacitive coupling the voltage at RT/CLK will attempt to exceed the -0.3 / 3.6V limits at times.  Is it sufficient to protect the input to clamp with a 3.0V Zener diode?  That would only clamp to about -0.7V.  Is a Schottky diode necessary? Would even a Schottky be sufficient, as it still wouldn't clamp as closely as -0.3V?