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LM25574 sync duty cycle

Other Parts Discussed in Thread: LM25574, LM25575

The datasheet for the LM25574 shows the sync input signal as a pulse train.  Is there a limitation on the duty cycle of the driving sync signal?  Is there any problem driving the sync pin with a square wave?

If the sync signal is not active, does the drive to the sync pin have to be hi-Z?

  • Hi Marc,

    There is a limitation on the duty cycle. According to the datasheet the minimum pulse width is 15ns. There is no issue in injecting a square wave pulse. If the Syn signal is not active, It does need to be Hi-Z but you can place a capacitor to decouple it from your external source.

    Thanks,

    Anston

  • Can you provide a sample circuit for the sync drive (or description thereof), with specific values for capacitance, any series resistance, bias resistors, protection diodes, etc.?  My sync source would be a full swing 3.3V CMOS signal *referenced to a different ground*.  Should the capacitive coupling be directly to the sync pin, or to an open drain driver which then connects to the sync pin?

  • Hi Marc,

    I've attached a schematic for a circuit. Use this as your starting point to define the needs of your circuit.

    Thanks,

    Anston

  • My sync signal will be sourced from a much higher ground reference.  I just want to verify that no pull-down resistor or high-side clamp is necessary on the SYNC pin to prevent the waveform there from drifting upward and periodically losing sync?  As I understand it from the diagram in the datasheet, when the sync input is detected as a logic low, the internal circuity additionally drives the sync pin all the way to ground.  That should provide the necessary centering effect on the capacitor.

    Furthermore, it looks like if the low time of the sync signal is longer than the one-shot time, the internal reset cycle will repeat multiple times during the sync signal low time.  I assume that is harmless, and the chip gets a clean timebase nonetheless?

    Also, given my higher voltage reference for my sync signal,  is a high-side clamp needed on the sync pin to protect it from overvoltage during initial start-up?

  • I still need to verify that the suggested capacitive coupling will really work properly.  From the "simplified sync circuit" in the datasheet, it seems that the chip will hold the sync pin low for some time after it initially goes low.  If the chip is still holding the pin low when the sync signal goes high, that will charge the capacitor and make it impossible for the rising edge to register when the chip stops holding the sync pin low.  Unfortunately it doesn't seem possible to determine what will really happen from the simplified diagram of the chip.

    I have a very noise sensitive environment, and I need to have high confidence that the sync scheme will work properly, with no glitches.  The power supply will be in the inverting configuration, so the ground reference for the chip will be at -9V relative to my system (and sync) ground.  The sync signal will be 3.3V CMOS at 700 kHz.

    Can you provide further guidance?

    Thanks!

  • Hi Marc,

    The small signal diode can be BAT54. This diode provides DC restoration through the high pass filter. This permits the external oscillator to fail at high, low or high-Z. Do you have a board that you can implement this on for testing? 

    Thanks,

    Anston

  • Because the LM25575 input pin apparently has an active drive to ground, will that not charge the capacitor to the state where it will continue to hold the sync pin at ground when the internal circuitry reverts to weak pullup?  Note that the datasheet recommends that the pin be driven from an open drain source.

    I don't have a proto platform available, and would not have time to prototype this circuit before going to fab.

  • I am still trying to determine the answer to the above question.  As far as I can tell from the datasheet, if the external sync signal goes high while the LM25574 is still holding the sync i/o pin low, the DC blocking capacitor will charge to the new voltage difference, and when the LM25574 releases the low drive, the i/o pin will stay low rather than swinging high.  The datasheet doesn't provide any timing information about the internal "one-shot" that seems like it would cause this to happen.  There is also no explanation as to what effect holding the pin low would have on the timing cycle, aside from the capacitor charging issue.  The datasheet suggests that the sync pin be driven with a narrow pulse.  If the input pulse has a considerably longer duty cycle (e.g. 50%), will the chip still synchronize properly, even at high sync frequencies (500 kHz to 1 MHz)?

  • Hi Marc,

    Be aware that the Abs Max of SYNC is 7V. Therefore some additional upper clamp is strongly advised. This could be a 5.1V Zener to GND or a similar diode clamp to a 5V rail.

    Unfortunately, because of the dynamics of your input sync signal coming from a different supply domain, it would be advisable to thoroughly bread board your design using that driving signal. The SYNC pin is bi-directional and made to interface with parts from the same family. It is unlikely that our online simulation package will be comprehensive enough.

    Thanks,

    Anston

  • Hi Anston, thanks for your reply.  Managing the voltage domains I'm not concerned about.  However, I do need to find out about the duty cycle.  The datasheet shows the sync pin being driven by a short pulse.  What will happen if the sync pin is driven by a square wave?

    Also, what would happen if the sync pin were to be held low for an extended period of time?  Would the chip still operate, on its own clock?  Or would it shut down?

  • I would use a fast opto for the level shifting.  My first guess is that the sync signal must be

    floating when the sync goes away and that a square wave is OK.  I have sent an email to the

    designers and am awating a reply.

    F.D.

  • Input from Designers:

    1)      Can a square wave be used on the input?

    A negative edge on nSYNC initiates the 500ns forced off-time. I don’t believe there is any issue using a square wave input.

    2)      Should the sync pin by Hi-z if the sync goes away?

    “A clock circuit with an open drain output is the recommended interface between the external clock and the SYNC pin.”

    Hi-Z recommended; low-Z to ground should be OK.

    Thanks,

    Anston

  • Hi Anston, thank you for your reply.  I am somewhat uncertain how to interpret you phrase "Hi-Z recommended; low-Z to ground should be OK.".  I need something definitive; "should be ok" is not that reassuring.  In my design, if the sync source should fail in the low state, leaving the sync pin driven to ground, I need to know if the power supply will keep working (and do so without an output glitch).  If the supply were to shut down, my CPU would crash....