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TPS3801 guaranteed reset at 0V

Barry Weinberger1
Prodigy 40 points
Other Parts Discussed in Thread: TPS3801

Hello,

With the TPS3801 series supervisors, how can I achieve a guaranteed reset at 0V?

Nearly every competitor supports this specification with the addition of a 100K pull-down to GND (assumes input leakage current of resetting device is not exceeded).

However, none of the TI supervisors indicate this in their datasheets.

Thank you,

 

Barry

 

  • 0
    TI__Mastermind 40610 points

    Hi Barry,

    Unfortunately, because this is an undefined state, it is not characterized so we cannot guantee 0V RESET. Nonetheless, it is at such a low voltage that it does not turn on any load. Unless that is what the customer is seeing?

    Regards,

    Darwin

  • 0 in reply to Darwin Fernandez
    Prodigy 40 points

    Hi Darwin,

     

    Thank you for your prompt reply!
     
    I understand that 0V is an undefined state. However, the verbiage below is presented in nearly every supervisor datasheet.
    When VCC falls below 1V, the RESET output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS-logic inputs connected to the RESET output can drift to undetermined voltages. This presents no problem in most applications, since most μP and other circuitry is inoperative with VCC below 1V. However, in applications where the RESET output must be valid down to 0V, adding a pulldown resistor to the RESET pin will cause any stray leakage currents to flow to ground, holding RESET low. The resistor value is not critical; 100K is large enough not to load RESET and small enough to pull RESET to ground.
     
    Does TI still prefer to remain neutral or indifferent regarding this application?
     
    Thanks so much!
    Best regards,
     
    Barry