Hi,
One thing we are worrying is that how much EMI interference would TPS62360 create?
We have an 8-layer FR4 board, and we currently route the power supply part of TPS62360 entirely on the top side (SCL, SDA, SENSE, VSEL0/1 are on internal layers). On the bottom side there are digital signals (below 30MHz). On the intervening layers there are also some signal traces pass below TPS62360, but at least separated by TWO GND layers.
Quoting the datasheet:
“PGND, VIN and SW should be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND, VIN and SW. They create a flux which is determined by the switching frequency. The flux generated affects neighboring layers due to capacitive coupling across layers.”
and assume the 2.5MHz default switching frequency here:
I wonder if AT LEAST two layers of GND separation is enough to protect the signals beneath from TPS62360’s influence? This thought haunts because the datasheet repeatedly stresses that layout is particularly critical for switching converters. In another post, we asked whether the “optimal” EVM board design was the result of extensive computer simulation (Maxwell equation, EMI, etc.), and our actual concern there was not only about the TPS62360 module itself, but also its influence on other ICs.
Would TI say that this is on case-by-case basis because customers’ designs vary? But this question seems very pertinent to many real applications, because PCB space is always limited and we could not simply move other IC’s far away from the TPS62360 to avoid influence.
Could TI give any “experience” on this, likely particular “good” / “bad” examples? And is there a rule of thumb on how much layers of separation is enough to keep other ICs/signal wires safe from TPS62360’s influence?
Matt
