TPS2066 EN to OC timing

Could you explain more about the conditions? You mention "OC inactive" which indicates that the present state of OC is active (or low). When OC is low, the switch is in current limit or thermal shutdown.

Are you asking how long it takes OC to go inactive after EN is de-asserted if the switch was in either the current limit or thermal shutdown condition? Maybe a diagram or further information would help.

The OC pin has a deglitcher of ~8ms (from the EC table) and this applies to assertion or de-assertion.

1) IN is power up to 5V
2) 3.5ms delay
3) assart 3.3V EN
4) OC inactive timing (OC is pullup to 10Kohm)

I check output over current condition by current probe, but no OC and TS condition.
(150uF is connected to the OUT, but I do check remove it.)

In this case, Is the delay timing not related deglitch circuit?

If you need more information, if you OK, please e-mail directry.

Thank you for the feedback.

For the case you describe, starting TPS2066 into 150uF (no load) should not cause the OC counter to start (see Ioc_trip). You can see how only Ios (~1.5A) is reached in figure 7. You can see the relationship of Ioc_trip (~2.3A) to the OCx pin timing in figures 8 and 9 (with the ~8ms OCx deglitch).

Hope this helps.

Yes, I know this timing.

But, this timing is OC deglitch timing.

I need EN to OC timing at power on.

It seems most device have few delay, but few device have about 5ms delay.

Regards,

1346.TPS2066_EN2OC.pptx

This is test circuit.

There should be no activity on the OCx pin after EN goes active (see modified attachment). If you see something different on the EVM, please send a scope shot.

Purple=IN
Blue=EN
Green=OC

This is not EVM but our board.
And, Yellow is unrelated.
The 3.3V make from 5V(same as IN).
The EN and OC are pulled up same 3.3V.

Is this OC output abnormal?

Yes, that looks like abnormal behavior (OCx should come up with the 3.3V supply). Is anything else connected to OCx that could be keeping it low (such as another chip that has not been powered up yet)?

No, OC not connect any other device.

But, I think this timing is not written in the data sheet.

No, this timing will not be in the datasheet because it is abnormal and unexpected. Does this behavior occur on more than one board or continue to occur if the IC is replaced? I have ordered the TPS2066EVM and will try to duplicate the behavior in our lab.

I did have the TPS2066CDGN and took the waveforms below to show how the IC is supposed to work.

Thank you for support.

Your EVM is delayed 1.5ms(EN to OUT2).
Few of device of our board are delayed,but it seems that several tens of pieces device are delayed.

When the hardware want latch OC signal, how much time do we have to wait?
(EN to OC delay: EN active -> delay -> OC latch -> Error or not)

Thank you.

For your immediate question about delay, I would suggest 500ms minimum delay.

I really appreciate your support and comment.

I understood about delay timing.

Thank you,
PAN-M

1) IN is power up to 5V
2) 3.5ms delay
3) assart 3.3V EN
4) OC inactive timing (OC is pullup to 10Kohm)

Where is from the 3.3V connect to /OC via 10kohm? Is it the same 3.3V with EN? Or from other place?

The 3.3V is made from 5V by the regulator.
EN and /OC are pull up by each 10K from same 3.3V.

Thanks,
PAN-M

Tested TPS2066CDGN again, all behavior looks fine and the same as Eric provided wave. As for TPS2066, there is no EVM on hand and waiting for the ordered EVM. So now, recommended replace TPS2066 with TPS2066CDGN on your boards to simulate the same test.