LM3150 external FETs destroyed

Hello,

The LM3150 shouldn't be doing any weird things to the dead time. Though the circuit performance could be affected by noise. You mentioned that you have almost no input cap. You definitely need some input cap. You do have the input bypass cap on your layout and schematic and that is correctly placed as close to the IC as possible and it does shares the same ground as the low side FET source. So that is good. You should consider adding some bulk input cap in addition to this which could have some relaxed placement but should share the same ground plane as the low side FET.

Are the FETs failing at startup or sometime in to the normal operation? You could be seeing some large voltage surges if your input is not regulated and in the absence of the input cap. To see if there is any abnormal spiking you could probe the switch node with your scope bandwidth unlimited. The datasheet says that the SW node should be as large as required. If you're not loading the circuit with high currents for too long, you might not have a large heating problem. I'd suggest you to consider the routing of the switch node through all layers. With greater SW node area, you have greater voltage transients or higher dv/dts. Same applies to the VIn node. If heatsinking is not required, then you could keep all the power to one layer. Having an un-interrupted ground plane right below the power plane helps in re-circulating high frequency AC current better and keeping noise out of the system.

I hope this helps.

Regards,
Akshay

Hello,

at the moment we increased the input cap to a 4µ7 in parallel with a 100nF. I am afraid that the cap is to far away from the Vin pin, isn't it?

As you can see in the schematics cutout, we have 5x 3300µF bulk cap very close to the converter (in the layout cutout you can see two of the five caps).


I don't know if the FETs fail at startup or under normal conditions. We had the fails only an boards at our customers, I am not able to provocate the fail here in my office.

I already have measured the voltages at Vin and at the switch node, because I thought that the FETs died because of over voltage spikes. I have never measured any voltages over 26V, either in startup or in normal operation. The FETs we use, are rated to 40V, so I think that is no problem.

I will think about an uncut ground layer for the next design revision.


There is now the question why only the new boards die, at the moment we have ~70 old boards that are runing for years without any problems and ~35 new boards. Until now 5 of the new boards died, in some cases after working only for a week or two, in an other case after working for 2 month.

Can you see differences in routing and placement between the old and the new board cutout, that can lead to damaging the FETs, at the given circuit?

Can the paralleling of the output caps cause problems? On the old board there are 9x 4µ7/25V in parallel, on the new board there are 10x 4µ7/50V in parallel. This results in a lower total ESR at the new board, doesn't it?. Can this cause a problem?

Regards,

Simon

Hello Simon,

To answer your questions first, paralleling more output cap is never going to be a problem. If anything, you reduced the ESR further and quietened the Vout node. You are already using the ripple generator circuit to provide some amount of ripple at the FB node for regulation, so your output cap can be as low ESR as you want. Even zero if that was possible. Other than requiring a little more current at startup, more output cap is not going to harm the FETs.

I looked at the placements closely. There seems to be hardly much difference between the old and the new. But I do realize what the situation is with your input cap and its ground. Sometimes some problems are masked and give an illusion that everything is fine and they come out when you make a small incremental change. I am thinking this is that kind of a situation.

On a buck regulator, the input cap ground and the low side FET ground should be very close to each other and share the same ground plane. This loop carries a high frequency AC current which, if not bypassed, causes problems. On your layout you pointed out that C49 and C51 are far from the IC pin. They are indeed far and while they don't need to be close to the IC pin, they need to be close to the T6 FET. The source of T6 and the ground of C49 and C51 should be on the same plane. The bypass for your input pin on the IC is already well done. If you look at the EVM layout on page 7 of the user guide, you will see that Cin2, Cin3, M1 and M2 form a very tight loop and the grounds of Cins and source of M2 are very close to each other. Both of your layouts have the grounds separated on a different layer. As to why the old board functioned normally with this, I can't say. Maybe there were some failures but not enough to raise a flag? 

What I can suggest as another experiment is that you could expose some solder mask from the Vin node and ground node near the input bypass cap. C49 looks like a big cap and that could fit on the expose solder mask. You will have to remove the input bypass cap C58. But since you have another ceramic cap in its place, the IC should hold up and not complain too much. The issue we're trying to solve is the noise mitigation in the power path. You could even remove C105 to make room. C48 is a similar cap and is right next to it so it should be ok.

I hope this helps.

Regards,
Akshay

Hello Akshay,

thanks for your fast answer.

I think, I was a little unprecise in my last post. With the Vin cap I meant the cap C58 not the caps C49 & C51. I was a little afraid that this cap is to far away from pin 2 and the value of 1nF is for sure to low.

I can say for 100% that there was no fail on an old board.

We have done the experiment that you suggest already. But under the thought to increase the cap on Pin 2. On the last boards we delivered, I replaced C58 with a 4µ7/25V, exactly as you suggested :-), and mounted a 100nF directly at Pin 2, on top of the IC.
Until now I have heard nothing of this boards, so we can only wait what will happen...

Summing up, we have done the following:

1. We have changed the FETs to 80V typs (I don't think this fixes the problem, but we have done it preventiv)

2. We have changed C58 to 4µ7/25V

3. We have mounted a 100nF directly at Pin 2, on top of the IC

Can you see any other possible problem points on the layout?

Or things that we can do preventiv on the new boards we deliver?

I am currently doing the next design revision. When I have finished the new layout for the converter circuit, I would ask you to have a look at and give me your feedback.

Thanks for your support.

Regards,

Simon

Hello Akshay,

ok, I understand what the cap should do, but I don't think that it will pass out the noise of the power path in this case.

As I write in one of the last posts, the two inner layers from the board are 24V and GND. So the long path between the input cap ground and the lowside FET is on an inner layer directly between the vias of the input cap and the vias of the lowside FET. Or am I wrong?

Does the additional 4µ7 cap have an affect in this case?

In the meantime I finished the new layout of the converter-section for the next revision. I attached a cutout of the schematic and the board. Can you please have a look and give me some feedback about it.

Regards,

Simon

Simon,

The placement of the 4.7uF caps is good. It shares the same ground plane as the T6/lowside MOSFET. Having Vin on a whole plane is basically setting noise on the whole plane. You could do that, but how about having it on the third layer? You could have the second layer as an unbroken ground which could cycle any AC current to the shortest loop and keep noise away from the sensitive components. The caps you need are the input bypass caps which should be very close to the MOSFET and the bulk caps which can be a little away. You still need to bypass the Vin pin of the IC also, which I believe you haven't changed.

I hope this helps.
Regards,
Akshay