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TPS40055 Current Limit

Saied ZARGAR
Intellectual 1120 points
Other Parts Discussed in Thread: TPS40055

Have a customer trying to better understand the relationship of the Current Limit threshold versus opterating temperture of the IC.  Here is the CL threshold data they have collected:

  • 5A at 27C
  • 3.3A at 70C
  • 2.4A at 85C  

They have conducted tests make help understand the behaviour of TPS40055 at temperature. 

monitored the waveforms on pins 10, 12 & 13 (i.e. SW, LDrive & Hdrive) on a scope and looked at the relationships to each other to see if there is any indication of the CL function
  • One characteristic was that the pulses broadened slightly near CL.
  • Another characteristic was the increase in phase lag between the beginning of the pulse and the Scope trigger.
  • One other characteristic was the increase in the negative excursion of the noise voltage of the LDrive (Pin 10) at the beginning of its pulse (i.e. turn-off of the HDrive) - but this was in the nano-seconds timeframe. Not sure if the device was actually current limiting, or else it was thermal limiting.
  • Monitored the IC surface temperature, but again there was no big revelations between low current and high current - about 8C degrees rise in both cases.
 
The goal is to achieve a CL threshold of at least 4A at 85C.
  • 0
    TI__Guru 56985 points

    Saied,

    There are two components to this, possibly 3, and both are actually working against the current limit over temperature:

    1)       The temperature dependence of the offset voltage of the SCP.  The Offset Voltage (difference between SW and ILIM at current limit) increases (becomes less negative) with increased temperature, this decreases the sensed VIN – SW drop required to trigger current limit.

    2)       The temperature dependence of the Rdson of the high-side resistor.  The temp co of a typical MOSFET Rdson is +0.4% / C or a 23% increase from 27C to 85C.

    3)       The third possible component would be a loss of inductance over temperature.  Since I don’t have the inductor, I can’t comment how much this could be contributing.  Since the TPS40055 controller is using peak current limit detection, any loss of inductance would reduce the DC output current at current limit by half the change in ripple current.

     

    The major contributors are likely 1 and 2.

    Equation 15 from the TPS40055 datasheet includes the Vin – Vsw dependence of the offset voltage.  The -20mV maximum offset accounts for the full -40 to +85 temp range.  If you’re just concerned with 25 – 85C, Vos(max) is 38mV.

    For Rdson(max) you’ll want to include both ambient temperature rise of 60C plus self-heating temperature rise.  I typically estimate this as another 20% increase in the Rdson (50C max rise at current limit).  That would mean the Rdson would be 1.45x the value listed in the MOSFET datasheet at room temperature.

    Also, if the input capacitor is loosing capacitance at high temperature and the input ripple is increasing, the difference between ILIM and SW may be increasing dynamically and thus reducing the current limit set-point in terms of current.  This effect can be greatly reduced by increasing the Cilim value.  Cilim forms a capacitive divider with the ILIM pins ESD capacitance (about 10pF)  With a 100pF Cilim, about 1/10 of the input ripple reduces the current limit set point.  400mV of input ripple will reduce the current limit set-point by 40mV.  Increasing to Cilim to 220pF would reduce this impact to 20mV.