TPS54719 quiescent current

Hi Hoang,

The specification used for the devices is the non switching supply current. When measured in the manner you're mentioning the IC is switching and there is additional input current for switching the FETs. To measure the non switching supply current we typically pull the FB pin voltage above the internal reference to force the IC to stop switching. We specify it this way because devices can often work at many different switching frequencies which will vary this supply current. This is the best way to limit the factors involved in the measurement. Also when measuring the supply current to the IC< make sure you're not measuring current through the EN divider.

Hope this helps explain.

Best Regards,
Anthony

Mr. Fagnani,

I was measuring it with EN floating, higher feedback divider resistors, higher inductance value, etc. I am surprise that is the case since RT was specified at 84k--suggesting that is the operating frequency with the lowest quiescent current.

If that is the case, how do I determine the lowest no load quiescent current from the specification? How do I lower the no load current of the TPS54719.

Thank you

You have to understand the difference between "quiescent current" and "no load current".  Quiescent current is what the IC draws when not switching (not regulating an output) vs no load switching current.  When switching, the converter will always draw more current.  The IC specification drives the VSENSE pin so that the IC does not switch to get the "quiescent current" rather than the no load current.  You have to understand that these are two different concepts.

John,

OK got it. How do I lower the no load current?

Thanks

can you restate your question?  You can lower the load current by not having any load attached.  But that is still "no load input current" not "quiescent current" which is the current when the IC is not switching at all.  You can measure that by forcing VFB high above the VREF.

John,

What I meant was if I don't connect a load across the output of the regulator such that the only components connected at the output are the voltage divider resistors (VFB) and the output capacitors. I am assuming that is what you are referring to as the "no load input current". That is what I measured to be 1.28mA under the best condition that I was able to achieve. Is it possible to lower this? If so how?

A better question is if the load is drawing only about 2-3mA, how do I lower the input current without shutting down the IC. The application that I am using it for draws about 2-3mA when the device is sleeping. When it is awake it draws about 8.5A peak then decrease to a steady state of about 2A. I can't shutdown the IC because it would take some effort starting that device up again if it were shutdown due to no input power.

Thanks

As long as the device is switching, there will be circulating RMS currents.  Even though the  load current is "zero" the RMS current will be reflected in the input current  to the IC.  To measure the quiescent current you have to force the IC not to switch by forcing VFB high.  Does that make sense?

John,

That make perfect sense to me after your first post. What I am asking is that how do I lower the no load current. I know it will be higher than the quiescent current, now that I understood what quiescent current means and how it was measured. For example, I notice that using a higher inductance would decrease the no load current--I think this is because the amount of time the IC spend switching the circuit on decrease since the VFB reach 0.6V faster and shutdown the switching quickly. Also, I am a bit curious about what is causing that power dissipation? When the output capacitor charged up such that VFB is 0.6 or a bit higher, the switching should stop. What cause the switching to turn back on again? Leakage from the capacitor alone is insufficient for it to drain that much no load current.

Thanks

Since this is a synchronous converter it will sink current when there is no load on the output. Or in other words the inductor current will go negative. This is some of the RMS current John is referring to. This is why increasing the inductance will decrease the no load input current. With smaller peak to peak current ripple, there is less RMS current and less power loss.

Some of the additional no load current comes from switching the internal FETs so one way to reduce the no load input current is to operate at the minimum switching frequency. However as a result of reducing the switching frequency there will be an increase the RMS current because there will be higher peak to peak ripple. It would likely need to be a combination of lower switching frequency and larger inductance you will need to try to get the input current as low as possible.