UCC28630 audible noise

Can you provide some more information?

- Lmag value

- Rcs value

- Np/Ns

- Vout

- Wurth part number?

Do you have a UCC28630 EVM to refer to? For that EVM, most audible noise issues that had to be resolved were only in the very light load region - at heavy load it's very quiet - but how does it compare to your board?

Generally, audible noise is due to the transformer vibrating if its not properly glued or varnished. Or it could be due to loop stability or noise-induced jitter. But it sounds like you have all of those areas covered.

We also found an audible noise issue in a prior engineering version of the EVM that took a while to solve - the issue was not the transformer at all, it was a vertically-mounted PTH resistor in the RCD snubber!

So it's also worth checking for other sources/causes?

The Freq dithering for EMC may also be a contributor - the dither moves freq by +/-6.5%, bit the dither rate is ~167 Hz, i.e the repetiton freq of the dither pattern - perhaps this is what you can hear?

Thank You for Your reply.

Trafo is Wurth 750811644. It's "first approach", so it doesn't perfectly fit because of too small Lpri (Lmag) for desired Pout (about 20W), but it's not our concern at the moment. Lpri is 800uH, Np/Ns is 7.142, Vout is about 20V. Suggested Rcs was about 0R9, but beacause of relatively small Lpri I had to lower Rcs to satisfy both of sampling conditions, so Rcs is 0R5 now. This leads to exceeding saturation current during full (peak - 200%) power loading, but we can ignore it also. Unfortunately Ipk vs Line adjust feature may not function, because condition 17 (see UCC28630 datasheet) is not satisfied (could it be reason of noise??).

During tests I increased Rcs to 1R, to raise switching freqency. The Ubulk sampling condition was violated because of too short t_on, but nothing interesting happened, noise was exactly the same. Interesting, that noise issue doesn't affect Vout regulation regardless of Rcs (even at 1R0) and output load.

It's possible there is some problem with frequency dithering. Because of relatively low frequency of modulation it's hard to observe the envelope, but I've checked thoroughly Vout ripple with load and there is small periodic pattern about 200Hz. But, why is it audible? Why is it audible with no load? Trafo is tight glued/lacquered.

Unfortunately we have no EVM, it wasn't available and we decided to prototype our board.

Could You explain, which value of output current one can calculate using equation 20 (datasheet)? I made own component calculator in excel (because of sligtly different approach to trafo design) and noticed, that output power calculated from (20) is about twice nominal power, so I suppose eq. (20) is for peak overload current. Am I right?  

Best regards

mbr

The UCC38630 EVM has been re-stocked, and is now available again:

http://www.ti.com/tool/ucc28630evm-572

From the Wurth 750811644 spec, it looks like the core is approx. E20/10/5 size, so for 1.4 A, Np is in the region of 90-100. Np = 100 looks likely, this tallies neatly with the turns ratios to give Ns = 14 and Naux = 12.

Besides the low inductance, this transformer has a very high Np/Ns ratio, the voltage reflected to the primary will be very high, and will cause the current to ramp down quickly in the Flyback interval, making the flyback reset interval potentially too short - this will forcew the choice of Rcs and/or Lmag to be changed to ensure that an output sample can be taken.

The second issue is that the Naux is also very high, for approx. 20 V secondary output, the aux bias rail wil lbe running very high, about 16.5 V, too close for comfort to the UCC28630 OVP protection level.

If Rcs is so low, and the transformer is already not a good fit, the peak flux levels will be higher than they should be, and this could be making the audible noise worse.

It does sound like the audible noise may be related to the freq dithering, which has a 6 ms repetition period (167 Hz). However, once the load level drops far enough, the freq dithering is disabled - this happens below a load level of approx. 33% of Pnom, where Pnom is the 60 kHz/640 mV corner P4 as shown in Fig. 39 of the datasheet.

Is the audible noise still present when load is below this point?

There may also be some audible noise due to control loop jitter in pulse-width and/or freq - the position and grounding of the decoupling caps on CS and VSENSE pins might help.

I don't think the Ipeak adjust with line (Eqn 17) is significant, this should just cause line reg error, and maybe some difficulty at high line no-load regulation if Ipeak is too big.

Eqn. 20 calculates the CC limit, based on the assumption that the peak power required is 2x the nominal power, so the CC-limit should approx. coincide with 200% peak power, as you already figurted out.

I would suggest changing the transformer to one that is a better match to the electrical requirements, or wind your own transformer?

Attached design calculator uses a modified version of the file on the TI web. This allows the reflected voltage to be explicitly specified and modified, so is easier to tune the turns ratio.

This inidcates about 940 uH of inductance, Rcs of 0.62 ohm, and Np/Ns/Naux of 106/22/14.

0310.UCC2630_20V_20W_revised2.xlsx

Thank You for the reply.

I'm aware, that the main issue related to UCC28630 is to guarantee conditions for voltage(s) sampling. It can be achieved by two methods: increasing Lpri and increasing amplitude of primary current (by decreasing Rcs value). Additionally, one can lower turns ratio to increase demag time (for Vout sampling). Wurth trafo has rather high turns ratio and not very high Lpri and You are right - it's far from optimum, but it's suitable for the first check. We decided not to build our own transformer before the first, general assessment of UCC28630 operation, so we used undersized off-the-shelf transformer, providing it's operation with reduced load and proper peak flux amplitude (I know, that Naux is to high, but there is simple voltage limiter between rectified Vaux and the controller, sampling network is connected directly to aux winding of course). Switching mosfet and the snubber are matched to higher reflected voltage. Unfortunately, the noise problem appeared and You know the rest... With regard to Your question: yes, the noise is present regardless of the load (with heavier load is slightly louder but is present even with minimum load - in the mW range). Moving of operating point of the controller by changing Rcs (with supply and load unchanged) shows no change. Of course, there is possibility of unwanted coupling between very noisy nodes (like mosfet drain)and sensing network, but layout is carefully designed to avoid this. PCB is 2-sided. Should be better? 4-layer board, local groundplanes, mosfet shielding, plenty of vias to ground, etc.? 

In fact, there is very hard (=impossible) to find optimal off-the-shelf transformer for UCC28630 and power levels about 15-20W, because the controller needs rather unusual transformer with turns ratio significantly lower than typical design values for other controllers (for demag time), and with very high Lpri (please note, that Wurth's trafo is typical for rated secondary voltage and power). On the other hand maximum Lpri is limited by internal feedback loop compensation, to 2mH, so maybe there is no way to build 15W power supply using UCC28630? Can You confirm that operation at higher Lpri is not recommended? UCC28630 datasheet says: AC/DC supplies for nominal power 10W-65W. Relying on my calculations I cannot really imagine that. Could You tell us, what are the parameters of the transformer (Lpri only) for 10W nominal power, please?  

Best regards.

mbr           

Thank You for the revised calc. I've just done some calculations using revised design calc and verified it with my own calc. For nominal power values 10, 15 and 20W results are similar (I've calculated maximum steady state output power from LI^2 energy transfer at 640mV/60kHz) and maximum Lpri is about 2mH at 10W (within the feedback compensation limit), so forget my last question (BTW, what does the mysterious cell D20 say? It's always 1.6*Pnom). Unfortunately maintaining low turns ratio is crucial for the successful transformer (because of demag time, not reflected voltage - or maybe there's something I don't know?), so probably it will be replaced. Is it possible that high reflected voltage disturb Vout sampling, causing my problems with noise?  

Best regards.

mbr

The website now has a similar version of the Excel calculator, but it's slightly improved. The one I posted here before was given to me before it was fully tested/released, so maybe it still had some errors in it.

The caclulator is designed along the assumption that the boundary point between DCM/CCM should occur at minimum bulk cap level (i.e. at the trough of the ripple at Vinmin), at the rated continuous load (i.e. 50% * Ppeak). At the target modulator operating point is 640 mV/60 kHz at this point. The required inductance is then calculated to achieve this suumed target.

if the reflected voltage is adjusted, this will affect the duty cycle at Vinmin when the operation starts to go CCM, which will then forse a re-calculation of the inductance to account for the change in duty cycle.

The new calculator on the web now allows for the above assumption to be over-ridden - the input voltage where the BCM point occurs can now be changed to be as high as the user would like. This gives more flexibility to force designs to go more into CCM.

For the reflected voltage, for sure there is a window that should be targetted. Due to the IC internal limitations, the Tonmin limits the minimum reflected voltage, and the output sampling delay limits the maximum reflected voltage. But the upper/lower limits also depend on the values of Rcs & Lmag, whoch in turn will depend on the chosen BCM operating point.

I don't think the turns ratio requirement is that "unusual", most designs target about 120 V, and this wil lalways be a tradefoff between the rectifier voltage rating, sec peak current stress and primary MOSFET Vds rating and stress. Less stress on the primary means more on the secondary, a vice versa. But the allowed reflected voltage range can be widened by design to position the BCM point at higher input bulk voltage levle as noted above.

Regarding the internal voltage control loop and recommended inducatnce range, the uper end oof the range was set by the assumption that the IC would be deployed at power levels of 10-20 W upwards. However, at lower power levels, with higher magnetising inductance, the loop should still be ok - we have implemented some 10 W designs with about 2 mH, and they are perfectly stable. So it's hard to define an upper limit on the allowed inductance value. for sure there is not internal fixed limit.

For a 10 W design, the target inductance depends on the chosen BCM point and on the chosen Vreflected, and both can be adjusted to tailor the performance and also to better suit a target turns ratio or inductance range.

As to your question about cell D20, maybe it depends on your version of Excel how this will display. But it's supposed to look like the picture attached.

3583.snap.tif

The cell contains 3 radio buttons to choose the desired overload timer trip level. Assuming that the average nominal power is Pnom, then the CC limit will kick in at or slightly above Pmax (= 2 x Pnom). The overload timer will allow continuous overload operation at either 110% or 135% or 160% of Pnom, above this level it will time-out. Depending on the lower operationg power, the load can surge up to 200% of rated Pnom for short times, as logn as the average stays below the chosen 110/135/160% setting. The gate drive pull-down resistor value will allow the required continupous overload level to be chosen, in conjunction with the timer time constant (speed of internal timer ramp up/down).

I don't think that the transformer turns ratio & reflected voltage would be a cause of the audible noise, if the demag time requirement was not met, then this would result in poor regulation at no load (Vout would increase), and possible even cause output OV.

However, the transformer leakage inductance could be a possible cause - if the leakage is quite big, and the bias winding waveform is still ringing when the output sample is taken (at the 1.8 us point after winding reversal), then the voltage sample may vary a lot from sample to sample, due to slight variation in the leakage ringing - this disturabnce in the sampled voltage could be causing the loop to vary the demand up/down around the required operating point, causing more modulation of Ipeak or Fsw than there should be, and maybe inceasing the audible noise.

If the audible noise can be improved by removing the freq dither feature, there will a version of UCC28630 with freq dithering disabled (among other feature/options changes), this will be available in a couple of months. The UCC28632 will have no freq dither, no latching faults (except for internal and PIN faults), no X-cap discharge (so can also run from DC input), and will have adjustable CC-mode overload protection instead of the overload timer.

I hope this info helps, sorry for the delayed response.

Thanks,

Bernard

Hello Bernard,

Thank You for the reply. Taking into account, that off-the-shelf trafos I've tested are non optimal for the UCC28630 (and the main non optimal factor was, of course, turns ratio ;) ), I've decided to build dedicated transformer, based on the new Excel calculator results. Input parameters are: Nominal power=15W, nominal Vout=20V, calc output: suggested Lpri=1185uH, suggested turns ratio=4.88. My trafo has Lpri=1180uH and turns ratio=4.947 (94/19) and Lstray of about 12uH (effect of manual wound and two secondaries - primary is stacked of course). Vaux now is adjusted to proper value of about 12V (series aux voltage limiter, mentioned before, now is disconnected). Trafo works OK, output voltages are OK, ton/tdemag times and operating frequency are as expected, power limit is OK, too. BTW, my "excel" probably wrong formats rows, and mysterious cell D20 is not your cell D20, it is the cell with label "maximum steady state output power Pol" and it says 24W (15W*1.6), and it corresponds to overload power, I guess, but I'm not sure this power is for "steady state" (thats why I was confused). The gate drive pull-down is 3k9, so my power supply limits its power to value somewhere between 14 and 17W (i.e. switches off if overload persists and restarts). So, almost everything is OK. Almost.

The audible noise is still here. Moreover, there is significant ripple at Vout, about 400mV and 170Hz, thus either the controller is confused by ideally synchronised noise / ringing (at Vsense pin) or something is defective. Unfortunately I have no more time to investigate the phenomenon, I had to switch to another IC.

Thank You for your help!

Best regards.

mbr. 

Hi Mikolaj,

It's unfortunate to hear that you have had to move on to another IC.

If you want to send me some of your hardware, I can test it and try to find the cause and a solution for the audible noise?

Thanks,

Bernard

Hello Bernard

Thank you for the offer. There is no hurry now, another PS is almost prototyped and It's unlikely we will return to UCC28630, so finding the right answer is only a matter of curiosity now. My board is not in good condition, after many changes of components, "rerouting" of traces (by wire :) ) etc, but I have an idea: do you have access to "blank" or defective PCB's of EVB? Could you send/sell us one piece (maybe via Arrow Warszawa, Contrans TI or another representative)? The board has optimized layout I think :). so maybe populating my components on it will explain something? 

Best regards.

mbr

Since the EVM was not available when you previously enquired, I can organise to have one sent to you now. The output voltage 19.5 V is very similar, though the power level is higher. You can test the EVM and then port your own transformer to it, and modify resistor values as required to suit your power level and turns ratio.

If you email your contact details to me bernardkeogh@ti.com I will organise the EVM.

Thanks,

Bernard