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Using LM5017 to generate dual supply

Other Parts Discussed in Thread: LM5017, LM5017ISOEVAL, PMP, TPS54060

Hello,

I need to generate +/-15V from a 24V input. I came across PMP7941.2 reference design on LM5017 and use a modified LM5017ISOEVAL to generate +/-15V.

In case it matters, these rails are to power split supply transducer that generates +/-5V signal which will go to ADC (referenced on the same Ground)

Have a few questions regarding the application:

  1. I used the calculated value based on the calculated ratio for Rfbb and Rfbt but the output is lower than I expected under small load (2mA) condition. As such, I tailored it so that I get +/-15V under the same small load. When I simulate higher load (30-80mA), the output voltage changed to follow the output based on the calculated ratio. Does the calculated ratio for the regulation (V out) applies under load?
  2. I was trying to find any curve regarding the load regulation for this device but could not find it anywhere. Based on my initial test, the regulation on the primary output is approx. 150mV for 40-80mA load but the secondary output regulation is approx. 0.93 - 1.5V for the same load as the primary. Is this to be expected?
  3. Since the load on my intended application would be the same on both outputs (for the split supply transducer), the difference between the primary and secondary output is a bit of a concern. Is there a way to make the secondary output regulate a bit better?

Thanks

Samuel

  • Hello Samuel,

    Please have a look at the PMP 7993.3 reference design on TI website. It is a quad output Fly-Buck design with +/-15V and +/- 5V outputs.

    Here is the Link: http://www.ti.com/tool/pmp7993.3

    Regards,

    Sourav

  • Hi Sourav,

    Thanks for the reply.

    I had a look at the design but that reference design is not within our budget with the transfomers in it. The PMP 7941.2 is ideal for application if it works.

    Web bench suggested the following circuit (attached) and this is the guide that I tailored the evaluation board to.

    I have done further test and able to generate +15V (+/-100mV under different loads) on the primary side, but the secondary output varied between -12.5V and -14.5V depending on the load. Is there a way to regulate the secondary output better?

    Thanks

    Samuel

    CT Power Supply +24Vdc to +-15Vdc Supply Design using LM5017 (Webench Design 879849-27).pdf
  • Hello Samuel,

    You can try bumping up the secondary output caps. The ones given in the schematic  (attached in the previous post) seem too small. Try increasing the output caps. You can try 4.7uF or higher.

    Regards,

    Sourav

  • Hi Sourav,


    Thanks for the suggestion. I have tried replacing the output capacitor to a higher value (tried 4.7uF) but the load regulation is still the same.

    Was thinking of using the second LM5017 to generate the negative output. Is this possible?

    Regards,

    Samuel

  • Hello Samuel,

    Given that you likely don't need the negative rail isolated, you might want to check out SLVA369 and Figure 3 of http://www.ti.com/lit/ml/szzn001/szzn001.pdf. Here, the total split-rail output voltage is regulated by resistor divider back to the FB pin, improving regulation performance (particularly if the positive and negative output are equally loaded).

    Regards,

    Tim

  • Hi Tim,


    Thanks for the suggestion. Looking at the TPS54060 device, it might be what I am after. Just a confirmation, the device is referenced to the -ve output and ground output is in the PH pin through inductor and connected to the ground input? Can the LM5017 be configured this way?

    Also, would LM5017 be possible to use as inverting buck-boost topology?

    Regards

    Samuel

  • Yes, you can configure the LM5017 in this inverting buck-boost configuration.

    Unlike the non-synchronous TPS54060, the LM5017 is a synchronous regulator, and it can maintain CCM operation even at no load (to provide better regulation).

    The regulator GND pin is at the negative output rail so the effective input voltage (from VIN to GND) is now higher by the -VOUT level. This is a nice benefit of using a wide VIN regulator in that it can accomodate this larger effective VIN.

  • Hi Tim,


    Thanks for the suggestion. I have tried the inverting topology and it works well.

    As far as getting the efficiency high, I have tried several options in Webench but it looks like lowering the switching frequency improve the overall efficiency to some extent and I understand that choosing a low DCR inductor would lead to lower loss in the inductor. Is there anything else that can be done to improve the efficiency?

    Regards

    Samuel

  • Hi Samuel,

    As expected, a tradeoff of efficiency vs. size is achieved by adjusting the switching frequency. Choice of coupled inductor is important in terms of copper and core loss.

    Regards,

    Tim

  • Hi Tim,

    I have configured LM5017 as the inverting topology but have a few questions as I build them on several protoype boards:
    1. Is there an equation to determine how the rails are split between the +ve and -ve voltages? The voltages it generates based on LM5017 calculation is the total voltage of the two, but the regulation isn't quite balanced between the two outputs.
    2. Are they balanced based on the load applied on each output?

    Regards,
    Samuel
  • Hello Samuel,

    I have inserted a schematic that likely represents your implementation. With equal currents in the outputs, there is a slight imbalance from the diode drop D1.

     

    Regards,

    Tim

     

  • Hi Tim,

    Thanks for your prompt reply.

    I apologise for not providing the schematic but yes that is the arrangement that I have with Vin = 24V and Vout- = -15V. As you mentioned there, there are slight imbalance due to D1 drop at the Vout+. I'm assuming that the voltage is equally spread between the two minus the D1 drop?

    The imbalance that I'm seeing is actually worse in light load/ no load conditions. During moderate load of approx. 20mA on each output, the voltages are close to each other with a diode drop voltage on Vout+. However, at no load/small load condition, there are about 700-800mV difference between Vout+ and Vout- with Vout+ being the higher ones (+15.82V vs -14.92V). Is this behaviour expected for this arrangement?

    Thank,
    Samuel
  • Hi Samuel,

     

    For imbalance at light loads, you might review the spike energy associated with the leakage inductance of the coupled inductor.

     

    Regards,

    Tim

  • Hi Tim,


    Thanks for your reply. I do have another problem that I am hoping to get your assistance in solving it.

    Attached is the schematic of the LM5017 and the other regulator that I use on the prototype board.

    The problem I have is that this arrangement is somehow affect the other regulator that generates 5V and 3.3V, causing the 3.3V output to turn ON again during turn off period. I suspected that this topology is what causing this issue as the problem disappeared when LM5017 is turned OFF (refer to scope measurement attached). The strange thing is that the output of the 3V3 regulator (LDO) somehow is higher than the input (5V) which does not make any sense.

    I have tried turning the LM5017 OFF (by taking out R415 - hence disable the LM5017) and then the issue disappear in the other regulator. Because there were no problem with U401, I suspect that the turn off issue was caused by LM5017; especially because the topology used here is unique.

    I suspect that because the switching node is now connected to Ground point that is connected to the other regulator, this causes the misbehaviour I see in the other regulator. Would you agree or is there any other possible reasons on why the other regulator turns back ON?

    Thank you for your help.


    Regards

    Samuel Loho

    PSU Schematic:

    Scope Capture:
    Turn-off Problem with LM5017 active

    Where:
    Ch 1 (Yellow) = VCC_24V

    Ch 2 (Light Blue) = VCC_3V3

    Ch 3 (Purple) = U402 SW (D406, pin 6 of U401)

    Ch 4 (Dark Blue) = VCC_5V

     

    with LM5017 disabled:

    Where:
    Ch 1 (Yellow) = VCC_24V

    Ch 2 (Light Blue) = VCC_3V3

    Ch 3 (Purple) = U402 SW (D406, pin 6 of U401)

    Ch 4 (Dark Blue) = VCC_5V

     

  • Hi Tim,

    Did you have any chance reviewing the last question I posted? Otherwise can you point me to the right person to discuss the issue with?

    Thanks,

    Samuel

  • Hi Samuel,

     

    It's a good idea to connect a filter capacitor from the 24V input to the -15V rail (RTN of the LM5017). Perhaps you can send the PCB layout for review.

     

    Regards,

    Tim

  • Hi Tim,

    Thanks for your reply.

    Thank you for your suggestion, my initial test showed that when I connect the filter caps into the -15V rail, the regulator doesn't start up. However, it turns out to be caused by something else.
    What was the reason to do that?

    Please find the relevant part of the PCB layout below:

    Regards

    Samuel

  • Hi Samuel,

    We typically recommend a solid GND plane on layer 2 (inner layer 1) immediately below the power stage. The capacitor as recommended carries provides the high frequency current for the MOSFETs and is thus connected from high-side drain to low-side source (i.e. VIN and RTN pins of the LM5017). For more information on PCB layout, you can review my EDN article series at this URL http://www.edn.com/design/power-management/4439695/DC-DC-converter-PCB-layout--Part-1.

    Regards,

    Tim

  • Hi Tim,

    Thanks for your reply.

    As you can see in the PCB layout I attached in the last reply, Inner layer 1 is GND plane and placed directly below the switcher. I have also followed the recommendation of putting any decoupling capacitor close to the pins (i.e. C424 placed close to U402 RTN pad, C425 close to the BST and SW pin, C426 close to VCC pin)

    The only direct connection between LM5017 and the other switching regulator is the UVLO pin that connects to 3V3 and the GND connection (as being -15V output) although when I tried to connect the UVLO pin direct to the input voltage (VCC_24V), the 3V3 rail turn on again like shown in the scope capture before.
    What I don't understand is how the 3V3 rail (an LDO) turn on again with the input (VCC_5V) is less when the LM5017 is enabled and the problem disappeared when I disabled LM5017.


    Regards

    Samuel

  • Hi Tim,

    With this topology, is there a way to turn off the regulator using UVLO pin? It looks like because the chip is referenced to -15V, negative voltage needs to be applied to the UVLO pin.

    Regards
    Samuel
  • Hello Samuel,

    Yes, the IC’s GND is effectively at –VOUT so the converter’s disable signal is not referenced correctly. You can use an NPN transistor to interface with the ENABLE logic signal and then level shift using a PNP transistor to the EN input. NPN/PNP dual “RET” parts are available to achieve this in a small footprint. Note that the precision enable function is lost in this case - it's only useful for converter enable and disable.

    Regards,

    Tim

  • Hi Tim,

    Thanks for your reply. The idea that you mentioned works.
    I have made an NPN/PNP circuit that controls the L5017 which enables and disables the regulator as you mentioned.

    To share with others in case somebody require this, the control circuit is made of two parts: NPN transistor controls the level shifter of PNP transistor. I managed to somehow control the enable function by biasing the NPN transistor with the input voltage, then using PNP transistor to level shift between -Vout and +5V.

    Regards

    Samuel