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LM3402MRX/NOPB

Other Parts Discussed in Thread: LM3402

Hi Sir,

I'm using the LM3402 part. Please help to advise below question.

What is the maximum allowable voids on the GND pad – thermal pad (Pin DAP)?

From 

Jason

  • HI Jason,

    I am not sure I understand your question. That being said, when we make our EVM's we try to optimize the layout for thermal performance. See the link here:  http://www.ti.com/lit/ug/snva175c/snva175c.pdf

    I know it is nearly impossible to duplicate the EVM layout for your system, but the more copper you can put under the device, the better.

    I hope this helps.


    Regards,

  • Hi John,

    Based on the datasheet page 2, the connection diagram as show below:-

    What is the maximum allowable voids on the GND pad – thermal pad on DAP Pin?

    Regard's

    Jason

  • HI Jason,

    If I am understanding your question properly, the meaning here is that the power pad DAP is very small so they recommend having a larger copper pour on the back side of the board to help spread the heat. See below:

    Then on the bottom side of the board:

    Does this answer your question?

  • Hi John,

    Actually what I would like to know is about solder void. Not about vias.

    How many % is acceptable for the ground pad? As per IPC this is to be defined between manufacturer and user.

    Therefore for manufacturer point of view, how many % of solder voids is acceptable for the GND pad (pin DAP)?

    Regard's

    Jason Teoh

  • From my experience working from the IPC-A-610 standard, "manufacturer" refers to the party assembling the boards, not the component manufacturer.  My book says, "The thermal transfer plane acceptance criteria are design and process related" which seems to mean that depending on the customer's usage of the part, the acceptability of thermal solder void may differ. It is up to the customer, their engineers, and the manufacturer (the board assemblers) to determine appropriate requirements based on the part's usage.  This usually requires destructive stress tests with varying levels of solder void to determine what is acceptable for the given application.