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BQ24163 IC SDA/SCL/INT Logic Levels

Hello, sorry if this has been brought up. I searched the forums and could not find anything covering this (which is surprising). In the datasheet for the BQ2416x series of charger ICs, section 9.5.1 it says the following about the I2C lines:

"The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL."

Yet, in the typical application example, Figure 21, there are clearly EXTERNAL pull-up resistors shown on the SDA, SCL, and INT lines. They are pulled up to 1.8 V on this schematic. Which is it? Do I need to regulate a 1.8 V rail just for these pull-ups and then level shift to my MCU (3.3 V logic level) or is it true that the I/O pins are pulled up internally and open-drain will suffice? There should be no other devices on this bus, it will connect directly to the MCU.

This isn't clear in the datasheet at all. Thanks!

  • Just wanted to answer my own question. It was a long day, and I was overlooking it (fellow engineer found it):

    Page 9, minimum logic level of SDA, SCL, and INT is 1.3 V. Therefore 3.3 V is acceptable, I believe it goes up to 7 V.