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LM3489 switching frequency

Go
Genius 4220 points
Other Parts Discussed in Thread: LM3489

Hi,

My customer is using LM3489 under the following conditions

Vin=12V  Vout=6.2V Iout=1A and the sw frequency become around 250kHz.

and they changed the FET to which had a lower Rdson and higher gate capacitance

(changed On-semi CPH3355 to ROHM RQ1E050RP ) 

As the result,  the Sw frequency was reduced to around 150kHz.

Is there any possibility that the FET specs make such a big impact on Sw frequency?

and the pin layout of these 2 FETs are different, so they jumpered between LM3489 PGATE pin and RQ1E050 GATE pin.

Actually I'm more concerned about an impact from the jumper.

Any advice would be appreciated.

Thanks

Go

  • 0
    TI__Intellectual 2320 points

    Hello Go,

    Ideally the gate trace length between the PGATE pin and the gate of the PFET should be as tight as possible. Adding a jumper introduces an additional parasitic inductance at the PFET gate which will impact the PGATE voltage (gate to source voltage) leading to issues like increased SW rise time or/and unwanted voltage transients at the gate. A proper board layout without the jumper will be a better approach.

    As mentioned in the LM3489 DS, in the MOSFET selection section, an increase  in the gate capacitance  leads to a decrease in the switching frequency. The increased gate capacitance as is the case in your circuit leads to increased SW node transition times and hence subsequent decrease in frequency.

    Regards,

    Sourav

  • 0 in reply to Sourav.Sen
    Genius 4220 points

    Hi, Sourav

    Thank you for your advice, and I'd like to ask another question about Cff value.

    Is there any recommended range of Cff value ?

    Thanks

    Go

  • 0 in reply to Sourav.Sen
    Genius 4220 points

    Hi, Sourav

    How is the follow-up question about the range of Cff value going?

    Your advice would be appreciated.

    Thanks

    Go

  • 0 in reply to Go
    TI__Intellectual 2320 points

    Hello Go,

    'Regret the late reply.
    The CFF helps in applying the full output voltage ripple at the FB node without any attenuation due to the resistor divider. Ideally the typical value of the CFF is around 470pF with the value being decreased linearly with increase in the switching frequency as given in the DS in page 11.

    Two good approaches to calculate the CFF would be to make sure the cut-off frequency of the pole due to the high side feedback resistor and the CFF is placed at roughly 1/10th of the the switching frequency.

    • (1/(2*pi*R1*CFF) = FSW/10. With this you should be able to get 4 times more ripple at the FB pin for the same output ESR. In other words you can reduce the ESR by four times to have the same ripple at the FB pin.
    • Another improved approach we use for COTs generally is to use CFF>=5 / (FSW*(R1 || R2)) and RESR >= 25mV / (Inductor Current ripple at min Vin).

    However, you can start with the first approach and move to the next one if needed.

    Hope this helps.

    Regards,

    Sourav

  • 0 in reply to Sourav.Sen
    Genius 4220 points
    Hi, Sourav

    Thank you for your advice.

    Regarding the "FSW" in the formula "(1/(2*pi*R1*CFF) = FSW/10",

    Does FSW mean that the actual Sw frequency before placing the CFF or the expected Sw frequency after placing the CFF?

    Thanks

    Go
  • 0 in reply to Go
    TI__Intellectual 2320 points

    Hello Go,

    FSW here is the actual desired switching frequency.

    Regards,

    Sourav