TPS54226 Power Good Functionality

Adam Swanbery

Other Parts Discussed in Thread: TPS54620, TPS54226

I am confused as to when the TPS54226 Power Good signal is clamped to ground on powerup. In other devices such as the TPS54620, the Power Good signal clamps to ground when Vin reaches 1V. In my design the TPS54226 Power Good signal is pulled up to the VREG5 using a 150Kohm resistor. On some boards I see a 8us glitch on Power Good after the EN goes hi, coinciding with VREG5 rampup. There appears to be a race condition between the VREG5 turn-on and Power Good clamping. The glitch can be removed by reducing the VREG5 capacitor from 1uF to 470nF.

The TPS54226 datasheet states "The power good function becomes active after 1.7 times soft-start time". Is this when the Power Good clamps to ground or when the clamp is released, or both? When does VREG5 turn on?

over 8 years ago

0 JohnTucker over 8 years ago

TI__Guru**** 191445 points

VREG5 turns on (starts to ramp up) when EN is above the EN threshold. When EN is high PWRGD is active. It will be held low during slow start until 1.7 x the slow start time. So for the 0.7 x slow start time, Vout is in regulation, but PWRGD is held low.

Can I see a waveform of the glitch you observe?

0 Adam Swanbery over 8 years ago in reply to JohnTucker

Prodigy 30 points

This first image shows EN in blue and PG in yellow.

The second image shows VREG5 in blue and PG in yellow.

Sorry, I only have a 2-Channel oscilloscope. Please let me know if you need additional waveforms.

0 JohnTucker over 8 years ago in reply to Adam Swanbery

TI__Guru**** 191445 points

It is difficult to see what is happening w/ 2 ch scope. looks like EN is tied to 3.3 V bus. What is VIN doing?

0 Adam Swanbery over 8 years ago in reply to JohnTucker

Prodigy 30 points

Here is a schematic of the 1.8V supply circuit. Vin is 8.0V (labelled 12V) and is stable long before the Enable input goes hi. The 1.8V PG output is wired to the PG output of a 2.5V supply, also a TPS54226. The 2.5V supply comes up several milliseconds before the 1.8V supply.

0 JohnTucker over 8 years ago in reply to Adam Swanbery

TI__Guru**** 191445 points

I have not been able to reproduce this. See the screen shot below, CH1 = EN, CH2 = PG, CH3 = VREG5. But I may have an idea about what is happening. the gate drive to the PG FET is derived from VREG5 internally. There may not be enough gate drive available. Does decreasing the PG pull up help?

0 Tom Schultz over 8 years ago in reply to JohnTucker

TI__Expert 3665 points

Hi John,

I spoke with one of the engineers and he had the following question.

When you asks “does decreasing the PG pull up help” do you mean decrease the value of the pull-up or the strength of the pull-up?

I am assuming based on your comment that the PG FET does not have enough gate drive that the idea is to reduce the pull up strength by increasing the value of the pull-up. Please confirm.

As I mentioned below, we are moving forward with the mod we have. We have actually only recorded this behavior on one board. If we get additional boards that exhibit this problem then we can experiment with the pull –up value.

Thanks,
Tom

0 JohnTucker over 8 years ago in reply to Tom Schultz

TI__Guru**** 191445 points

I was suggesting to decrease the resistor value. If you only see this on one board, how many total?

0 Tom Schultz over 8 years ago in reply to JohnTucker

TI__Expert 3665 points

John,

There were 5 boards total.

Tom

0 JohnTucker over 8 years ago in reply to Tom Schultz

TI__Guru**** 191445 points

If I read this correctly, the glitch is only about 300 mV. Is that going to be a problem for you? I think in most cases, that would still be interpreted as a "low".

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TPS54226 Power Good Functionality