I have a new design using a pair of TPS54394 regulators to supply the following rails.
Reg 2: 1.0V@2A and 1.5V@1A
We are using the recommended power inductors, ceramic input capacitors, and ceramic load capacitors for each rail as suggested in the data sheet. These are located close to the regulator per the layout recommendations. In addition there are additional bulk capacitors placed on the PCB near the loads themselves which in this product are a video SoC and an FPGA. Additional bulk capacitance is in the range of 6-10x 10uF ceramics. In addition, there are a large number of 'small' 1.0uf, 0.1uF, and 0.01uF capacitor distributed around the load pins.
Power distribution is via solid planes and the loads are 3-5 inches away from the regulator. It is likely there are significant load transients during operation.
We seem to be observing excessive supply ripple (noise). The observed ripple is about the same across the output capacitors at the regulators as is observed across the bulk capacitors near the loads. In some cases we see 200mV p-p which is out of spec. It varies on each rail but eyeballing it on the scope the spectral content of the supply noise appears to be in the 200kHz to 1MHz range.
It is not uncommon for reference designs for this type of FPGA to use large 220-330uF low ESR POSCAP (or similar) on the core supply rails.
Our reading of the DCAP2 compensation suggests that in order to keep the loop stable the load capacitance must be kept with a certain range - not too small and not too large. Our inclination is to both increase the capacitance and reduce the ESR of the bulk loads but we wanted to understand what limitations there might be. The SwitcherPro software doesn't support this particular device and when trying to model using similar devices it doesn't provide plots for stability analysis.
What are your recommendations?
