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LM3409HV-Q1 Battery Voltage Drop(Cranking) Capability

Other Parts Discussed in Thread: LM3409HV-Q1, LM3409, TINA-TI

Dear, Sir. 

My customer is evaluating LM3409HV-Q1 for LED lighting source on HUD

application. As you know, Short time battery voltage drop at engine

restart after idling-stop(Cranking)must be mediate under real usage. 

The customer is asking about such capability of LM3409HV-Q1. 

Below is Vin(Battery voltage) profile at cranking. 


PS) Output is just 1 LED, around 3.4V/1A.

1. I wonder LM3409HV-Q1 could work correctly during Vin voltage drop and after that?

2. I concern VCC Regulator driving which is defined on the DS(Vin > 9V, 0 < Icc < 20mA).

   Is it no problem during Vin voltage drop? 

Best Regards, 

H. Sakai

  • It should work ok as it will not be below the VCC UVLO threshold, but as it is out of spec none of the datasheet numbers could be guaranteed during that time interval. It will recover just fine from a voltage dip when VIN comes back up.
  • Dear, Clinton-san. 

    Thank you so much for your reply. 

    I would like to confirm your mentioning little bit more. 

    1. Vcc spec is ; min 5.5V, typ 6V, max 6.5V. 

        If Vin = 5V, Vcc Regulator could not generate the proper voltage which

       is defined on the datasheet. It may affect to the decrease of iLED(LED

       current) although depend on the external PMOS FET parameter. 

       It is just my guess, How do you think about that? 

    2. Vcc UVLO is defined typ. 3.73V(Vcc increasing). 

       I wonder Vin value across the threshold could be estimated? 

    Best Regards, 

    H. Sakai

  • Yes, below a certain input voltage VCC will be out of regulation and if it is low enough you may not get full enhancement/output current depending on the Vgs of the FET used. As for what the VCC is in dropout, that will depend on how much VCC current you are using due to the FET gate charge and switching frequency. The linear pass element could have an Rdson of about 75 ohms at high temperatures, so if you need VCC to drive 10mA the VCC voltage will be 750mV less than your input voltage.

  • Dear, Clinton-san. 

    I appreciate your valuable information. 

    May I confirm several things?

    1. Vcc-UVLO(increasing) = typ. 3.73V and Vcc-HYS = 0.283V

        So, Vcc-UVLO(decreasing) will be typ.3.447V. 

        If VCC to drive 10mA, Vin across Vcc-UVLO(decreasing) will be 

        4.197V (3.447V + 0.75V).  Vin 5V is over Vcc-UVLO(decreasing) threshold. 

        I wonder it is the reason why you mentioned "It should work ok as

        it will not be below the VCC UVLO threshold" on the previous mail?

    2. Following is the my assumption about behavior after checking LM3409 

        TINA-TI Transient Reference Design(snvm421. tsc). I modified just 1 LED

        as the output on that. 

        Could you agree that? 

        a) Almost of PMOS FET VGS(th) will be max. -4V. So, VGS(th) will be no

            problem under Vin 5V. 

        b) On snvm421.tsc, 2N6845 is applied as external PMOS FET and Iload(peak) = 2.5A. 

            VDS = 5V because Vin is 5V. 2.5A could not drive by 2N6845 due to 

            Id limitation influencing VDS & VGS. 

            LM3409 looks working under "NEAR DROPOUT OPERATION" (Iload = 1.2A)

            described 15page on the datasheet. 

        c) When 2N6845 is changed to 2N6849(more powerful Id under VDS = 5V

            & VGS), LM3409 will continue the switching(normal operation even if 

            Vin 5V. 

    Best Regards, 

    H. Sakai

  • 1. That is correct.

    2. That should be fine, however the OFF time will increase (switching frequency will decrease) since the off timer is connected to the output. This will reduce your gate drive current requirements, but it will increase the current ripple. You may need to readjust for your application requirements.

    2a. Yes.

    2b, c. The difference in behavior between the two is most likely due to the Rds(on). The 45 FET has twice the Rds(on) so it will drop twice the voltage and enter 100% duty cycle mode before the 49 circuit will. One you are in 100% duty cycle mode the LED current is simply determined by the input voltage and the drop across the FET.

  • Dear, Clinton-san. 

    I am feeling a mount of gratitude for all of your helpful and valuable


    At last, I would like to make sure a kind of trigger the mode was transferred 

    from normal switching to 100% duty cycle. 

    CSP & CSN pins are monitored by an internal comparator for IL-MAX control

    determined by external Rsns.

    if Id current of PMOS was reduced due to Vin drop(reduced VDS) and  averaging

    IL-MAX became out of control, then LM3409 entered 100% duty cycle mode. 

    I wonder above understanding is correct? 

    Best Regards, 

    H. Sakai

  • That is correct. But it can happen at any Vin depending on Vout, not just low Vin. If while switching the current peak cannot be reached it will enter 100% duty cycle mode. The Rds(on) of the switch will help determine when this happens as it produces a voltage drop, but at low enough Vin that the gate drive is reduced it will happen even sooner since the Rds(on) will increase.

  • Dear, Clinton-san. 

    I am feeling a mount of gratitude for all of your valuable information

    and teachings. 

    Everything has been cleared in my side. 

    Could you please teach me again if there were additional. 

    Thanks a lot. 

    Best Regards, 

    H. Sakai

  • No problem. As long as it pertains to LED drivers (except backlighting) I can probably help.

  • Dear, Clinton-san.

    Thank you so much for your current support.

    I obtained the schematic of customer designed.
    Is it possible let me know your private e-mail for me?

    I would like to get your advice if some improvement was needed
    after sending it for you.
    I am very sorry because the schematic is a kind of confidential.

    Best Regards,
    H. Sakai