UC3825A related question

Dear Jacky,

The CT and RT are used together to determine the PWM frequency. If you look at the data sheet on page 6 in the middle left of the page, there is a graph showing the frequency of the pwm vs. the RT and CT called Timing Resistance vs Frequency. My guess is that if you have 10K ohm RT and 220pF causes the PWM frequency to exceed the capability of the IC.

Hi Chuck Sampson:
thanks,
During my test , if the RT is 2.7k and CT is 150P, the OUTA/OUTB output are abnormal.
if the RT is 1.8k and CT is 220P, both output are normal.
But the PWM frequency are same at both configuration.
it seems that CT value is the key factor.
i'd like to know how the CT causes the OUTA output abnormally.


Best wishes,
Jacky

Jacky,

I tried to up load my answer. But as you see I have had no success. None of the graphs are visible.  I hope TI improves the ability of it forum editor so that we can more easily upload files and graphs. In the meantime I have sent you my answer directly through email.

Regards,

Chuck

 

Hello Jacky,

I will try to answer your question as best I can. I am not the IC designer of the UC3825, so to know exactly what is going on inside the chip you would have to ask him, or a TI rep. That being said, there are standard circuits that are usually found in every PWM IC and the RC oscillator circuit is one of them. The snippet below shows the portion of the UC3825 block diagram concerned with the clock oscillator and the RT CT components.

 

 

 

The circuit above is found on page 6, just above the Timing Resistance vs Frequency graph. It is a more detailed representation of what is in the block OSC in the graph above it.

The circuit is somewhat confusing because a lot of detail is left out. The data sheet writers want to give out as much information as they can about the IC to help the user, but without disclosing everything so that their competitors cannot copy their solutions.

The most confusing part is the current source IC = IR. The schematic does not show the actual circuit, which I suspect is a current mirror. There are many types of current mirror circuits and they are all optimized for specific applications. I suspect the details of this circuit are left out for either brevity or proprietary reasons or both. The current mirror circuit is well documented and you can google it to learn exactly how it works. To understand how RT and CT affect the clock signal all you need to know is that the current in the RT resistor shows up in the IC source. The current in the RT resistor is obviously 3V/RT.

The clock circuit is based on the same principle as the Schmidt trigger, or relaxation, oscillator. A current source, represented by IC, charges up CT until V (CT) is greater than the Schmidt buffer input threshold. When V (CT) exceeds the buffer threshold, the output of the buffer goes high and turns on both of the NPN transistors. The NPN transistor that has its collector connected to CT turns on and begins discharging the timing capacitor, CT, and reducing V(CT). We will refer to this transistor as the “discharge transistor”.

The NPN transistor connected to pin 4 also turns on, so that the voltage V(4), or V(Clock), is near zero volts, or in a “low” state. We will refer to this transistor as the clock transistor. The discharge transistor reduces the value of V(CT) at a controlled rate determine by the values of RT and CT. Once V(CT) returns to a value below the Schmidt buffer input threshold, the buffer output goes low and both the discharge and clock transistor go to a high state. One cycle of the clock oscillation is completed. Because the discharge transistor is back to its original off state, the timing capacitor starts recharging due to the current in IC and the cycle repeats.

The rate at which V(CT) charges and discharges is determined by the current IR that flows through the transistor collector sourced by IC. If RT is of the highest value on the timing chart, IR is at minimum, than the discharge transistor turns off slowly. For a given CT, the frequency of the V(Clock) signal is minimum. This assertion is verified by the Timing Resistance and Frequency Chart. Looking at this chart and focusing on the 100 nF line, one can observe that as the RT increases in value, the V(Clock) frequency decreases.

 

 

 

If you look at the chart and observe where the two blue lines intersect, you will see where your RT and CT values approximately lie on the chart. So it appears that you are trying to drive the V(Clock) frequencies much higher than it is capable of providing. That is why you are get “abnormal” output. You need to use RT CT combinations that are shown on the chart above.

Good luck with your design,

Chuck