Hi all,
A customer has a question about the TPS65279 and features associated with its PGOOD and EN pins. Data related to the questions have been shown on datasheets for similar parts, but not on the 65279 so I wanted to clarify two main things.
1. Is there hard info/numbers on the PGOOD delay for the device? There is a start-up sequence scope grab in the datasheet, but it only shows Vout1, Vout2, and EN voltages, leaving out PGOOD. The electrical characteristics table shows 94% "PGOOD trip level" for "FB rising to PGOOD high", but I'm not sure what to make of this in terms of a calculation or observation on the graphs.
2. Can the EN pin be delayed with a capacitor from EN to GND while EN is being used for UVLO adjsutment? This method is mentioned in the TPS65251 datasheet, but I wanted to verify that it would work for the 65279. My guess is that the delay would be significantly shorter (per nF) due to the resistive divider also charging the capacitor, rather than the internal weak pull-up itself.
Thanks for the help!
Justin
