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LM43600 Design Startup Unstable

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Other Parts Discussed in Thread: LM43600

I have implemented a WebBench design of the LM43600 with +24VDC input and a +12V output with .5A max load. The circuit starts up correctly most of the time. But when starting cold there is an occasional instability that resembles starting and stopping every ~20msec. Here's a (blurry) picture.

But most of the time the circuit works correctly, like this.

Here's the web bench design

The layout is tight and should not be the problem. Here's a view of the layout.

Unfortunately, with even the slightest possibility of a startup problem, we can't use this design. Can anyone recommend some sort of fix?

  • MikeH,

    I am going to move your post to the product line forum. They should be able to better assist you with this problem.

  • Hello,
    Please send us clear pictures of the SW node, inductor current (if possible), and VOUT during startup. The softstart is about 5ms long. So please zoom out on the scope and capture that image.

    While the layout is tight, it needs a few improvements. Here are some comments on the layout:
    1) There need to be more vias on the VCC ground
    2) The C36 is your input capacitor and it's ground should be as close as possible to the ground pins of the IC (pins 15 and 16). The way you have it now causes the noisy input current to travel a long loop to get to the PGND pins on the IC.
    3) You haven't shown your VOUT sense trace to BIAS pin and top of upper feedback resistor. It should be away from the SW node.
    4) Where is your bias cap? It should right at the BIAS pin. The bias pin is an input to an internal LDO. The BIAS cap is bypass for noise to that input.


    Regards,
    Akshay
  • Akshay,

    I have attached a series of snapshots of the startup voltages. 

    The first shot is of Vin and Vsw. Note that Vin ramps slowly from 0 to +24V over a ~500 ms time. There is not way to improve this since the board has several very large capacitors on it.

    Also note, the scope probes are 10X so the voltage readings are 10% of the actual values.

    The next shot zooms in on the startup time period and shows switching beginning when Vin reaches ~2.9V. However, the switching stops again a short time later (see next shot).

    Here's a zoom of the initial 1.67ms. Note that Vsw averages ~2.2V while Vin is at 3.2V. The switching stop after ~1.67ms.

    And here's a similar sequence of Vsw and Vout.

    Here Vout is ~4V and never goes higher.

    This start/stop repeats every 7.4 ms.

    Here's another look at the first 1.7ms.

    Here's a look at the end of the first 1.7ms.

    I'll post another post concerning the PCB layout.

  • Regarding the PCB layout:

    1) There need to be more vias on the VCC ground

    The board is a 4-layer board with a VCC and GND plane under the entire area. The VCC and GND vias should be OK. More might be better, but I believe the existing vias are not the problem.

    2) The C36 is your input capacitor and it's ground should be as close as possible to the ground pins of the IC (pins 15 and 16). The way you have it now causes the noisy input current to travel a long loop to get to the PGND pins on the IC.

    Since the vias run to a GND plane under the entire circuit, the GND vias should be adequte.

    3) You haven't shown your VOUT sense trace to BIAS pin and top of upper feedback resistor. It should be away from the SW node.

    4) Where is your bias cap? It should right at the BIAS pin. The bias pin is an input to an internal LDO. The BIAS cap is bypass for noise to that input.

    C39 is the bias cap. The via on the right side of C39 runs on the bottom layer back to via below C37. Very short run and away from the SW node.

    FYI, I soldered another bias cap directly on the via below C39 to ground. It did not help.

    I'm starting to think that the long ramp up time of my VCC is causing the issue. I'm just not sure why.

  • Hi Mike,

    This looks like you might be entering the hiccup mode of the part because of the charging current for your output capacitance.
    Based upon the fact that you are only reaching 4V and want to reach 12 I would suggest adding a capacitor to the soft start pin to slow the rise time of the output voltage by a factor of at least 3 or 4. So first pass try a 47nF capacitor on the soft start pin.

    Regards,
    Marc
  • You could also look at adding an input voltage divider on the EN pin so that the part starts up at a higher input voltage.
  • Marc,

    It was definitely entering hiccup mode. It's because of the very large capacitive load that the chip is driving (~2400 uF). I added a 1uF to the SS pin and haven't had a false start since.

    There is an interesting pause in switching as the output voltage ramps. it's happening at ~75ms after trigger when the output voltage reaches ~3v.  Not sure what's happening, but it's worrisome. Any ideas?

  • Hi Mike,

    Its hard to say without seeing the output current profile,

    This part will lower the switching frequency quite a bit based on load. Since the soft start time is very slow, its possible the output voltage jumped slightly above the soft start reference voltage so the part lowered the switching frequency to avoid overshooting.

    Do you have a spot on the board to measure load current?

    Regards,
    Marc