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TPS84610 INH internal resistor values

TIguru
Expert 1430 points
Other Parts Discussed in Thread: TPS84610

Hi,

   What are the internal resistor values tied to the INH pin in a TPS84610 device?  I am currently using an open drain buffer, 74LVC2G07, connected to the IHN pin and I want to make sure this open drain device is not causing unintended glitching on the output.  From the datasheet, INH pin "has an internal pullup. Do not place an external pull-up resistor on this pin. If this pin is left open circuit, the device operates when input power is applied. A small low-leakage MOSFET is recommended for control. See the application section for further guidance."

What is the maximum leakage value for the MOSFET?  Does my open drain buffer meet the spec?

In advance, thank you.

  • 0
    TI__Mastermind 28020 points

    The TPS84610 has an internal resistor divider of 48.7kΩ (top) and 34kΩ (bottom). We typically recommend a low leakage FET with 100nA - 200nA of leakage current.

  • 0 in reply to J Arrigo
    Expert 1430 points

    Hi Arrigo,

       Thanks for your response.  

    Our schematic and layout shows that we run these INH/UVLO lines all over the board, and out to the test connector.  We would like to determine if we can break the rule about “not providing an external pullup” on this input line.  I see that this set up to carefully control the current through the internal divider for use in the Under Voltage Lock Out (UVLO) function (my assumption).  Since touching a high-Z scope probe to INH can cause TPS84610 to turn off, we need to confirm that we can force the pullup current to a higher level.

     With the high impedance divider, the current is only at 61µA with Vin=5V.  The values show that the voltage sitting on this pin will be 2V with Vin=5V.   The data in the table below shows for Vin=3.3V, that the typical UVLO threshold on a decreasing Vin is at 2.75V.  This 83% of Vin.  If Vin=5V, then this threshold value becomes 4.2V.  So if a glitch appears on this control input that takes this voltage down to 4.2V, the regulator will begin to shut down.  I imagine for a short glitch that the regulator output voltage will track the glitch and come back quickly, but then the damage is done in terms of the supply voltage going to our critical chips (switch, PHY, FPGA, etc.).   

    Please advise if we can safely add an external pull up to prevent TPS84610 from turning on. Please confirm that the only issue with providing an external pullup is that the UVLO function will be affected.  We’re only looking to use this control input as an on/off control line from our processor – we’re not concerned with the UVLO function.  I would like to run a test with a pullup at 470 ohms.  Our drivers can easily handle 10mA during power up where we hold these regulators off until we’re ready for the voltages to be present.  We need to kill any possible glitches on these lines.

    In advance, thank you for your help.

  • 0 in reply to TIguru
    TI__Mastermind 28020 points
    It will be OK to add an additional pull up resistor to the INH/UVLO pin. However, the Abs max on this pin is 3.3V, so make sure the added resistor does not cause the voltage on this pin to exceed 3.3V. Use a value of 30kΩ, or larger.
  • 0 in reply to J Arrigo
    Expert 1430 points
    We will try a 30K for the pullup. Another question – if what determines the spec is the Vmax 3.3V at this pin, could we put an additional divider external (2 resistors) to keep the voltage at 3.3V, but decrease the overall resistance? Example: use a 1K pullup, and a 2K pulldown. Calculating this divider in parallel with the internal divider gives us just under 3.3V, but at a larger current through the external divider, making the noise problem much less. Please see if this is also a possible solution.
  • 0 in reply to TIguru
    Expert 1430 points

    One more question:

    We are thinking of bypassing the INH/UVLO pin with a cap to ground.  Any restrictions on adding a capacitor on INH pin?  Thinking of something like a 0.1 uF.

    Again, thank you!

  • 0 in reply to TIguru
    Prodigy 5 points

    I think a filter cap on INH UVLO is something good to try for a noisy signal coming to this pin.
    A filter on a UVLO input is common in power circuits.
    I see no reason why it would cause a problem.

    0.1uF may be too large, try to use the smallest one you can and still get noise filtered out.

  • 0 in reply to Ed Walker
    Expert 1430 points

    Thank you for your response Ed.  We will try smaller capacitor values until we find the correct threshold for solving our issue.