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tps54418, 100% duty cycle

Nicolas Bruneau
Prodigy 490 points
Other Parts Discussed in Thread: TPS54418

Hi,

I'm looking to using tps54418 for a low drop operation which consist of 5.5Vin, 5.2Vout, 3.5A=Iout, Fsw=1MHz.

I have used and tuned the standard tps54418EVM to do some preliminary measurements in order to validate the concept.

I have started the tps54418 at light load and the setup seems to work fine HOWEVER when I increase the load, Fsw fold back to around 333kHz for Iout=3.5A (full load condition).

  • This frequency-foldback is mentioned for the startup and OC (over current) in the datasheet, but nothing say that it could happen as well when we hit close to 100% duty cycle. So it’s a bit ambiguous…
  • I saw another information in the datasheet which indicates that the tps54418 can work up to 100% dutycyle as long as the Boot to PH voltage doesn't drop below the Boot UVLO threshold. For tps54418: Vuvlo(boot)=2.1V typ for Vin=3.95V. So I have measured the Boot to PH voltage, see below.

Blue trace = BOOT to GND
Yellow trace = PH to GND
Note = We clearly see that the 2 switching cycles on the left are at 500kHz (Fsw/2), then the 3rd one is around 333kHz (Fsw/3).

Looking at the screenshot above it doesn’t seem that the Bootstrap capacitors isn’t charged enough. So no problem to be foreseen from this side...
Therefore I would suppose that the internal frequency foldback is causing this frequency shift.

Could you comment and put some lights on this mode of operation? it's not clear when this frequency fold back can happen and which Fsw is then applied on the Switching Node.

Thanks and best regards,
-nico

  • 0
    TI__Guru**** 191445 points
    Increasing duty cycle above 100% will cause the perceived switching frequency to be reduced. That is by definition.
  • 0 in reply to JohnTucker
    TI__Prodigy 490 points
    Depends how you see it.
    There are dc/dc that will drive the high side switch continuously at some points, limiting the duty cycle to 100% . No frequency jump is observable on those.

    I'm also surprised that the frequency drops by a factor 3. This is quite a change that can impact the output filter design.
    Can you provide explanations and calculations in order to understand how this frequency fold back mechanic is implemented?
  • 0 in reply to Nicolas Bruneau
    TI__Guru**** 191445 points

    Frequency foldback as described in the datasheet is an entirely different phenomenon.  TPS54418 uses peck detect current limit.  When the switch current reaches the current limit threshold, the On time is terminated and the duty cycle is reduced.  With lower than required duty cycle, the output voltage will drop along with the fed back output voltage at VSENSE (normally 0.8 V when the circuit is in regulation),  When VSENSE falls to a nominal 0.6 V, the frequency is reduced by 25%.  When VSENSE falls to a nominal 0.4 V, the frequency is reduced by an additional 25%.  When VSENSE falls to a nominal 0.2 V, the frequency is again reduced by an additional 25%.  See figure 7 in the datasheet.  The general idea is that the on time stays the same, but the off time is greatly increased.  The switch current is allowed to decrease during the off time much more than it would at the nominal.  Switching frequency.  It will never be reduced by a factor of 3 as you observe.

    I would expect that what you are seeing is not frequency foldback due to current limit.  If it were you should see the output voltage reduces as above.  I think that as you lower the input voltage towards the out put voltage the duty cycle is increasing.  Increasing the load current also causes the duty cycle to increase.  At some point you are going beyond the nominal 100% duty cycle.  The high side can stay on until either the control loop is keeping the circuit in regulation or the BOOT charge runs out.  Either of these cases will cause the effective switching frequency to decrease.  If you are planning on intentionally running in these conditions, then you will need to design your output filter with that in mind.