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LM25066IA Over Current Fault

Other Parts Discussed in Thread: LM25066IA, LM25066, LM25066I


I'm trying to prevent an over current fault condition from switching off the MOSFET using a LM25066IA. I understand the risk of doing this in my design, but I have other protection in my design to prevent any damage.

I'm able to use the PMBus to set specific registers to prevent this fault:  Register D7h =04

I can then apply a load that would trip the over current fault, and my design will restart (turn off). Measuring the Timer and Gate pins; it goes through the restart sequence and there is still a very small glitch on the gate. I don't believe the glitch would cause the MOSFET to switch OFF. Additionally, I'm using the PGOOD pin to perform power sequencing down stream and this pin is being pulled down when the over current condition is experienced. 

Do I have all the PMBus registers changed to prevent a over current fault condition from switching the MOSFET off?

Should the PGOOD get pulled down in this condition?

Can the over current fault be preventing using the LM25066IA? The datasheet for LM25066 does not state the ability to do this but the LM25066IA does.

Thank you!

  • Chad,

    Gate / Alert masking is mainly intended for system debug during a system validation (Engineering).  It is highly recommended that Gate Mask not be used for production.  Gate mask will still set the registers and send an SMBA/.  Alert mask (D8h) will block the SMBA/ but the fault registers will still be set.  Per the DS's, the LM25066 does not allow gate mask where the IA verions does.  Current limit timer activates per the programming resistor on the timer pin, and Vout will be lowered as needed to regulate to the programmed current limit (25mv or 46mv) and is load impedance dependent.  PGood will activate if Vout drops below the threshold set on the FB pin due to this current regulation (likewise if Vin drops below the UVLO).  If you want to adjust the realized current limit setting higher than the 25mv or 46mv and use the same shunt, you can use a divider resistor (ex: 10ohm and 2 ohm to fine tune).  A small capacitor on the Vin-Sns with these resistors can filter this a little (don't go over 1usec TC).  Defeating Current limit and CB protection (Gate Mask) will most likely result in FET failure.  Gate Mask (bit 3) for I-In also disables the Power Limit protection that can result in FET failure during power up or most likely during a Power Into Short after a down stream fault.  CB protection is in the 1usec response range.  If any longer, not only is the FET stressed, but I-in can rise to very high levels and when the 'other' protection you have kicks in, a very high voltage can occur at the input due to this di/dt * line inductance and damage to the LM25066IA can happen. 

    Make certain a beefy TVS and Schottky are used at input and output per the apps information.  Assure you have a robust SOA window FET in your design.

    Regarding Glitches, when placing the Vin capacitor, place it directly on the input side of the Rshunt, not at the LM25066IA.  Inductance in the etch to the LM25066IA will filter the signal seen by the + sns and you will see an impact for current sense because the -sns will see the full glitch.  May cause current sns error and may cause Vin - Sns to exceed data sheet max voltage if not placed right at the shunt.


  • I understand and am accepting all consequences for gate masking the over current fault protection.

    Since that LM25066IA will support over current gate masking. Is this the only register that needs to be changed: Register D7h =04?
  • You can maintain the CB (bit 0) at either 1.8x or 3.6x if desired. With Gate mask, you will still get the SMBA/ (alert) unless you change the appropriate bits in Alert mask (D8h). I believe this is how it will all work, best to give it a look under actual conditions.

  • Are there any registers other than D7h that need to be changed to allow my design to ignore an over current condition? Possibly another register that puts the LM25066IA into a mode where it ignores the pin connections and uses the register settings?

    Do you know if gate masking of the over current condition has been successfully masked?
  • Chad,

    Updated after reviewing. CL and CB gate mask are not functional on the 'Gate Mask' Register for any of the LM25066 variants. This was removed from the LM25066 DS and will be on updated LM25066I/IA and 'A' DS's. The options available are 46mv CL and changing CB from 1.8x to 3.6x, or using a resistor divider with small filter as noted.