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How Much Current Can the UCC28C40 Reliably Source?

Other Parts Discussed in Thread: UCC28C40

Hello,

I would like to know if it is acceptable to utilize the VREF output to selectively (through P-FET in series with a diode) drive the RT pin of the UCC28C40 to hold it in the disabled state. Otherwise stated, can the VREF supply provide the required current to oppose the ~8mA RT/CT current sink to hold the node high. Essentially we want to utilize a microprocessor control that can both provide an external sync (or free-run) the PWM when VCC is present, or automatically gate a HIGH to RT/CT when VCC initially comes up to hold the PWM off. We don't want to back-drive the part through the RT/CT pin when VDD is not present.

The two options I'm investigating right now are the attached (see below), and a version of the attached with the AND gate replaced with the P-FET described above. The P-FET option obviates the need for us to add a new part type to the BOM provided the VREF can source the needed current. Otherwise the AND gate ensures we have adequate drive to oppose the current sink. I do not want to drive 8mA through the MPU GPIO directly.

Please let me know if it is safe and acceptable implementation.

Thank you in advance,

Chris

  • Chris,

    The VREF pin is rated to be able to supply at least 30 mA (see VREF output short-circuit in the UCC28C40 datasheet). So it should be possible to hold RT/CT pin high with a PFET. However, I would recommend that you either breadboard or simulate your circuit to be sure before you commit to PCB ordering.

    Alternatively, you can also hold the PWM IC in an off state (no PWM output at OUT pin) by pulling the COMP pin low. Since the COMP is the output of a transconductance amplifier, it's inherently current limited and it's safe to short to GND. And since there is an offset from COMP to CS, there is min level on COMP below which PWM will be inhibited - the COMP only needs to pull below 1.15 V ( COMP to CS offset) to inhibit PWM, so it can be pulled low through a diode.

    Regarding SYNC functions and interfacing to the RT/CT pin, I would recommend this thread too, that user ran into trouble when trying to drive the RT/CT pin too:
    e2e.ti.com/.../517513


    I hope this info helps.

    Thanks,
    Bernard
  • Bernard,

    Thank you very much for the speedy reply. Oh, how did I not see that in the datasheet!?

    I will most certainly breadboard the solution. I actually have a P-FET to our 3.3V rail in there right now and it's working fine. We also have had this (working) design in place for many years. It's only in this latest incarnation that we have the need to hold off the PWM when the primary rail first comes up. So it's an incremental tweak, so to speak. We've also been considering interfacing to either the COMP or FB pin as a mechanism to disabling the part (i.e. pulling FB high or COMP low as you've stated).

    Thanks again and I will let you know what we end up going with.

    Regards,

    Chris

  • Hi Bernard,

    I'm starting to lean towards your suggestion regarding driving the COMP pin low through a diode as it seems to present the least complexity. The one concern I have with this is that the error amp output is limited at 10mA. So I'd still be sinking 10mA into a single MPU GPIO pin when driving the cathode low. What do you think about driving the FB node high through a diode instead? Since the FB node is a high impedance input to the error amp, very little current will be required. When the control is later driven low to enable operation the diode will block any noise via the control line.

    Regards,

    Chris

  • Hi Bernard,

    I've attached our final implementation below. I decided to go with the initial implementation with one minor addition of a 100K pull down on VREF to ensure it is not floating at t0.

    Thank you for your help. Everything appears to be working just fine on the bench here.

    Regards,

    Chris