Hello,
I would like to know if it is acceptable to utilize the VREF output to selectively (through P-FET in series with a diode) drive the RT pin of the UCC28C40 to hold it in the disabled state. Otherwise stated, can the VREF supply provide the required current to oppose the ~8mA RT/CT current sink to hold the node high. Essentially we want to utilize a microprocessor control that can both provide an external sync (or free-run) the PWM when VCC is present, or automatically gate a HIGH to RT/CT when VCC initially comes up to hold the PWM off. We don't want to back-drive the part through the RT/CT pin when VDD is not present.
The two options I'm investigating right now are the attached (see below), and a version of the attached with the AND gate replaced with the P-FET described above. The P-FET option obviates the need for us to add a new part type to the BOM provided the VREF can source the needed current. Otherwise the AND gate ensures we have adequate drive to oppose the current sink. I do not want to drive 8mA through the MPU GPIO directly.
Please let me know if it is safe and acceptable implementation.
Thank you in advance,
Chris